Cryogenic Computer Architecture Modeling with Memory-Side Case Studies

Modern computer architectures suffer from lack of architectural innovations, mainly due to the power wall and the memory wall. That is, architectural innovations become infeasible because they can prohibitively increase power consumption and their performance impacts are eventually bounded by slow memory accesses. To address the challenges, making computer systems run at ultralow temperatures (or cryogenic computer systems) has emerged as a highly promising solution as both power consumption and wire resistivity are expected to significantly reduce at ultra-low temperatures. However, cryogenic computers have not been yet realized as computer architects do not fully understand the behaviors of existing computer systems and their cost effectiveness at such ultra-low temperatures. In this paper, we first develop CryoRAM, a validated computer architecture simulation tool to incorporate cryogenic memory devices. For this work, we focus on 77K temperature (easily achieved by applying low-cost liquid nitrogen), at which modern CMOS devices still reliably operate. We also focus on reducing the temperature of memory devices only as a pilot study prior to building a full cryogenic computer. Next, driven by the modeling tool, we propose our temperature-aware memory device and architecture designs to improve the DRAM access speed by 3.8 times or reduce the power consumption to 9.2%. Finally, we provide three promising case studies using cryogenic memories to significantly improve (1) server performance (up to 2.5 times), (2) server power (down to 6% on average), and (3) datacenter's power cost (by 8.4%). We will release our modeling and simulation tools deliberately implemented on top of only open-source simulators combined, even though some experiments were conducted under industry-confidential environments.

[1]  Kevin Skadron,et al.  HotSpot 6.0: Validation, Acceleration and Extension , 2015 .

[2]  John L. Henning SPEC CPU2006 benchmark descriptions , 2006, CARN.

[3]  Yukikazu Iwasa,et al.  Case Studies in Superconducting Magnets: Design and Operational Issues , 1994 .

[4]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[5]  Sally A. McKee,et al.  Hitting the memory wall: implications of the obvious , 1995, CARN.

[6]  J. Arblaster,et al.  Thermodynamic Properties of Copper , 2015 .

[7]  Sharad Singhal,et al.  Adapting to Thrive in a New Economy of Memory Abundance , 2015, Computer.

[8]  Ricardo Bianchini,et al.  Page placement in hybrid memory systems , 2011, ICS '11.

[9]  AilamakiAnastasia,et al.  Clearing the clouds , 2012 .

[10]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[11]  Moinuddin K. Qureshi,et al.  Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study , 2017, MEMSYS.

[12]  Manoj Sachdev,et al.  Impact of technology scaling on thermal behavior of leakage current in sub-quarter micron MOSFETs: perspective of low temperature current testing , 2002 .

[13]  Kunle Olukotun,et al.  A Single-Chip Multiprocessor , 1997, Computer.

[14]  J. A. Morrison,et al.  The heat capacity of pure silicon and germanium and properties of their vibrational frequency spectra , 1959 .

[15]  R. Schaller,et al.  Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).

[16]  Francis Balestra,et al.  Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperatures , 1987 .

[17]  Babak Falsafi,et al.  Clearing the clouds: a study of emerging scale-out workloads on modern hardware , 2012, ASPLOS XVII.

[18]  Hongliang Zhao,et al.  Modeling of a standard 0.35μm CMOS technology operating from 77K to 300K , 2014 .

[19]  Yuan Taur,et al.  A 4 Mb Low-temperature DRAM , 1991 .

[20]  Sally A. McKee,et al.  Do superconducting processors really need cryogenic memories?: the case for cold DRAM , 2017, MEMSYS.

[21]  G. Ghibaudo,et al.  Low temperature characterization of 14nm FDSOI CMOS devices , 2014, 2014 11th International Workshop on Low Temperature Electronics (WOLTE).

[22]  William D. Callister,et al.  Fundamentals of Materials Science and Engineering: An Integrated Approach, 2nd Edition , 2004 .

[23]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[24]  Zhihua Gan,et al.  Measurement of boiling heat transfer coefficient in liquid nitrogen bath by inverse heat conduction method , 2009 .

[25]  Norman P. Jouppi,et al.  Heterogeneous chip multiprocessors , 2005, Computer.

[26]  Yonggang Wen,et al.  Data Center Energy Consumption Modeling: A Survey , 2016, IEEE Communications Surveys & Tutorials.

[27]  Randall Barron,et al.  Cryogenic Heat Transfer , 2016 .

[28]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[29]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[30]  P. Liley,et al.  Thermal Conductivity of the Elements , 1972 .

[31]  V. Semenov,et al.  RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems , 1991, IEEE Transactions on Applied Superconductivity.

[32]  Thomas Vogelsang,et al.  DRAM Retention at Cryogenic Temperatures , 2018, 2018 IEEE International Memory Workshop (IMW).

[33]  Edward J. Nowak,et al.  Maintaining the benefits of CMOS scaling when scaling bogs down , 2002, IBM J. Res. Dev..

[34]  R. Schaller,et al.  Moore's law: past, present and future , 1997 .

[35]  Jung Ho Ahn,et al.  CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[36]  Naoki Takeuchi,et al.  An adiabatic quantum flux parametron as an ultra-low-power logic device , 2013 .