In Situ Training of CMOL CrossNets

Hybrid semiconductor/nanodevice ("CMOL") technology may allow the implementation of digital and mixed-signal integrated circuits, including artificial neural networks ("CrossNets"), with unparalleled density and speed. However, previously suggested methods of CrossNet training may be impracticable for large-scale applications of these networks. In this work, we are describing two new methods of "in situ" training of CrossNets, based on either genuinely stochastic or pseudo-stochastic multiplication of analog signals, which may be readily implemented in CMOL circuits. The methods have been tested by numerical simulation of CrossNet-based perceptrons by error backpropagation on three problems of the Probenl benchmark dataset. The testing gave very encouraging results: CMOL CrossNets with their binary elementary synapses may provide, after the in situ training, classification performance at least on a par with the best results reported for software-based networks with continuous synaptic weights.

[1]  Konstantin K. Likharev,et al.  Electronics Below 10 nm , 2003 .

[2]  Yasuji Sawada,et al.  Functional abilities of a stochastic logic neural network , 1992, IEEE Trans. Neural Networks.

[3]  Lutz Prechelt,et al.  Automatic early stopping using cross validation: quantifying the criteria , 1998, Neural Networks.

[4]  Mark A. Ratner,et al.  Introducing molecular electronics , 2002 .

[5]  Konstantin K. Likharev,et al.  Neuromorphic architectures for nanoelectronic circuits , 2004, Int. J. Circuit Theory Appl..

[6]  Seth Copen Goldstein,et al.  Molecular electronics: from devices and interconnect to circuits and architecture , 2003, Proc. IEEE.

[7]  E. Oja.  Simplified neuron model as a principal component analyzer , 1982, Journal of mathematical biology.

[8]  Zhenan Bao,et al.  Control of topography, stress and diffusion at molecule–metal interfaces , 2005, cond-mat/0510371.

[9]  D. Strukov,et al.  CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices , 2005 .

[10]  S. Folling,et al.  Single-electron latching switches as nanoscale synapses , 2001, IJCNN'01. International Joint Conference on Neural Networks. Proceedings (Cat. No.01CH37222).

[11]  Dmitri B. Strukov,et al.  A reconfigurable architecture for hybrid CMOS/Nanodevice circuits , 2006, FPGA '06.

[12]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[13]  D. Strukov,et al.  Prospects for terabit-scale nanoelectronic memories , 2004 .

[14]  Lutz Prechelt,et al.  A Set of Neural Network Benchmark Problems and Benchmarking Rules , 1994 .

[15]  D. Strukov,et al.  CMOL: Devices, Circuits, and Architectures , 2006 .

[16]  Jung Hoon Lee,et al.  CMOL CrossNets as Pattern Classifiers , 2005, IWANN.

[17]  Alexander N. Korotkov,et al.  Correlated single-electron tunneling via mesoscopic metal particles: Effects of the energy quantization , 1990 .