Multiplier reduction tree with logarithmic logic depth and regular connectivity
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[1] A.P. Chandrakasan,et al. A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[2] Chein-Wei Jen,et al. High-Speed Booth Encoded Parallel Multiplier Design , 2000, IEEE Trans. Computers.
[3] Harold S. Stone,et al. A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.
[4] Christopher S. Wallace,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..
[5] Vojin G. Oklobdzija,et al. A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach , 1996, IEEE Trans. Computers.
[6] Earl E. Swartzlander,et al. Reduced area multipliers , 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).
[7] Andrew D. Booth,et al. A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .
[8] J. Vuillemin,et al. Recursive implementation of optimal time VLSi integer multipliers , 1984 .
[9] Earl E. Swartzlander,et al. Optimizing multipliers for WSI , 1993, 1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration.