Relation Between the Mobility, $\hbox{1}/f$ Noise, and Channel Direction in MOSFETs Fabricated on (100) and (110) Silicon-Oriented Wafers

A study of the impact of the channel direction over the effective mobility and the 1/f noise in MOSFETs fabricated on (100) and (110) silicon-oriented wafers finding its outcome in the fabrication of future nonplanar device structures has been done. We found that, apart from a slight enhancement of the effective mobility maximum for the p-MOSFETs with a channel along the 100 direction, the channel direction had no effect on the noise level and performances of the transistors when they are fabricated on (100) silicon-oriented wafers. This suggests that a slight but effective enhancement of the already existing CMOS technology is possible by fabricating the MOSFETs with a channel along the 100 direction. Regarding the (110) silicon-oriented wafers, the modification of the channel direction resulted in a change of effective mobility, with the enhancement being maximum for a p-channel along the 110 direction and an n-channel along the 100 direction. Whereas this came with a noise level apparently unchanged for the p-MOSFETs, a perceptible change has been noticed for the n-MOSFETs, with the devices with a channel along the 100 direction showing the highest noise level. Finally, for the Si(110) n-MOSFETs, the earlier limitation of the effective mobility coming from the surface roughness scattering led to a negative transconductance; for the first time, it was clearly shown experimentally that two different uncorrelated noise sources generate the 1/f noise, with one becoming predominant over the other. The first noise source, attributed to the fluctuation of the insulator charge inducing fluctuations in both flatband voltage and mobility, initially contributes by itself to the total 1/f noise, then decreases and lets the second noise source, i.e., the fundamental mobility fluctuations, come out. This strongly suggests that, in the MOSFET, both noise sources, the fluctuation of the insulator charge and the fundamental mobility fluctuations subsist together, with one covering up the other according to the physical characteristics of the device and to the bias conditions.

[1]  P. Llinares,et al.  Low frequency noise characterization in 0.13 mum p-MOSFETs. Impact of scaled-down 0.25, 0.18 and 0.13 mum technologies on 1/f noise , 2004, Microelectron. Reliab..

[2]  Cor Claeys,et al.  Impact of silicidation on the excess noise behaviour of MOS transistors , 1995 .

[3]  E. Simoen,et al.  On the 1/f noise of triple-gate field-effect transistors with high-k gate dielectric , 2009 .

[4]  J. Bokor,et al.  Low-frequency noise characteristics of ultrathin body p-MOSFETs with molybdenum gate , 2003, IEEE Electron Device Letters.

[5]  Tadahiro Ohmi,et al.  Total Room Temperature Wet Cleaning for Si Substrate Surface , 1996 .

[6]  Hisashi Hara,et al.  Mobility Anisotropy of Electrons in Inversion Layers on Oxidized Silicon Surfaces , 1971 .

[7]  S. Shimizu,et al.  Effect of <100> channel direction for high performance SCE immune pMOSFET with less than 0.15 /spl mu/m gate length , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[8]  C. Ciofi,et al.  Comparative study of drain and gate low-frequency noise in nMOSFETs with hafnium-based gate dielectrics , 2006, IEEE Transactions on Electron Devices.

[9]  Y. Morita,et al.  Atomic scale flattening and hydrogen termination of the Si(001) surface by wet-chemical treatment , 1996 .

[10]  J. Jomaah,et al.  Coupling effects and channels separation in FinFETs , 2004 .

[11]  B. Tavel,et al.  Can 1/f noise in MOSFETs be reduced by gate oxide and channel optimization? , 2005 .

[12]  F. Hooge 1/f noise sources , 1994 .

[13]  H. Mikoshiba,et al.  1/f noise in n-channel silicon-gate MOS transistors , 1982, IEEE Transactions on Electron Devices.

[14]  F. Hooge 1/ƒ noise is no surface effect , 1969 .

[15]  F. Balestra,et al.  Shrinking from 0.25 down to 0.12 μm SOI CMOS technology node: a contribution to low-frequency noise in partially depleted N-MOSFETs , 2003 .

[16]  G. Guegan,et al.  Static and low frequency noise characterization in surface- and buried-mode 0.1 μm PMOSFETS , 2003 .

[17]  A. van der Ziel,et al.  Unified presentation of 1/f noise in electron devices: fundamental 1/f noise sources , 1988, Proc. IEEE.

[18]  Kyu-Hwan Shim,et al.  The low-frequency noise characteristics of p-type metal-oxide-semiconductor field effect transistors with a strained-Si0.88Ge0.12 channel grown on bulk Si and a PD-SOI substrate , 2008 .

[19]  T. Ohmi,et al.  Highly reliable ultrathin silicon oxide film formation at low temperature by oxygen radical generated in high-density krypton plasma , 2001 .

[20]  Jean Brini,et al.  Influence of quadratic mobility degradation factor on low frequency noise in MOS transistors , 1998 .

[21]  K. Romanjek,et al.  Low frequency noise characterization and modelling in ultrathin oxide MOSFETs , 2006 .

[22]  W. Saslow,et al.  Electrostatic screening near semiconductor surfaces , 2000 .

[23]  Mikael Östling,et al.  Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs , 2007 .

[24]  Tadahiro Ohmi,et al.  GEOMETRY AND BIAS DEPENDENCE OF LOW-FREQUENCY RANDOM TELEGRAPH SIGNAL AND 1/f NOISE LEVELS IN MOSFETS , 2005 .

[25]  G. Ghibaudo,et al.  Low-frequency noise characterization of n- and p-MOSFET's with ultrathin oxynitride gate films , 1996, IEEE Electron Device Letters.

[26]  A. Pirovano,et al.  On surface roughness-limited mobility in highly doped n-MOSFET's , 1999 .

[27]  R. Degraeve,et al.  Reliability Comparison of Triple-Gate Versus Planar SOI FETs , 2006, IEEE Transactions on Electron Devices.

[28]  Gerard Ghibaudo,et al.  Low frequency noise characterization of 0.18 μm Si CMOS transistors , 1998 .

[29]  Lode K. J. Vandamme,et al.  Noise as a diagnostic tool for quality and reliability of electronic devices , 1994 .

[30]  D. Schumann,et al.  Vertical N-channel MOSFETs for extremely high density memories: the impact of interface orientation on device performance , 2001 .

[31]  Peter Händel,et al.  Quantum 1/f noise associated with ionized impurity scattering and electron-phonon scattering in condensed matter , 1985 .

[32]  S. Takagi,et al.  On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration , 1994 .

[33]  A. Chou,et al.  Hybrid-orientation technology (HOT): opportunities and challenges , 2006, IEEE Transactions on Electron Devices.

[34]  Gerard Ghibaudo,et al.  Experimental characterization of the subthreshold leakage current in triple-gate FinFETs , 2009 .

[35]  Gerard Ghibaudo,et al.  Improved Analysis of Low Frequency Noise in Field‐Effect MOS Transistors , 1991 .

[36]  B. Kaczer,et al.  Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs , 2007, IEEE Electron Device Letters.

[37]  Marcel A. Py,et al.  Evidence for screening effects on the 1/f current noise in GaAs/AlGaAs modulation doped field effect transistors , 1996 .

[38]  Tadahiro Ohmi,et al.  Hot Carrier Instability Mechanism in Accumulation-Mode Normally-off SOI nMOSFETs and Their Reliability Advantage , 2007 .

[39]  Damage free very low electron temperature plasma process for low Flicker noise in p-MOS fabricated on (100) and (110) silicon-oriented wafers , 2009, 2009 Proceedings of the European Solid State Device Research Conference.

[40]  D. Schroder,et al.  Impact of post-oxidation annealing on low-frequency noise, threshold voltage, and subthreshold swing of p-channel MOSFETs , 2004, IEEE Electron Device Letters.

[41]  Tadahiro Ohmi,et al.  Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers , 2009 .

[42]  P. Solomon,et al.  Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness , 2003 .

[43]  L.K.J. Vandamme,et al.  1/f; noise model for MOSTs biased in nonohmic region , 1980 .

[44]  Mikael Östling,et al.  1/f noise in Si and Si/sub 0.7/Ge/sub 0.3/ pMOSFETs , 2003 .

[45]  M. Saitoh,et al.  Physical Understanding of Fundamental Properties of Si (110) pMOSFETs Inversion-Layer Capacitance, Mobility Universality, and Uniaxial Stress Effects , 2007, 2007 IEEE International Electron Devices Meeting.

[46]  Gérard Ghibaudo,et al.  Electrical noise and RTS fluctuations in advanced CMOS devices , 2002, Microelectron. Reliab..

[47]  S. Haendler,et al.  Low frequency noise and hot-carrier reliability in advanced SOI MOSFETs , 2004 .

[48]  A. Hoffmann,et al.  Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90 nm , 2004 .

[49]  S. Takagi,et al.  On the Universality of Inversion Layer Mobility in Si Mosfet's: Part 11-effects of Surface Orientation , 1994 .

[50]  T. Ohmi,et al.  Low noise balanced-CMOS on Si(110) surface for analog/digital mixed signal circuits , 2003, IEEE International Electron Devices Meeting 2003.

[51]  Eddy Simoen,et al.  Correlation between the 1∕f noise parameters and the effective low-field mobility in HfO2 gate dielectric n-channel metal–oxide–semiconductor field-effect transistors , 2004 .

[52]  T. Ohmi,et al.  Very High Carrier Mobility for High-Performance CMOS on a Si(110) Surface , 2007, IEEE Transactions on Electron Devices.

[53]  L.K.J. Vandamme,et al.  1/f noise in MOS devices, mobility or number fluctuations? , 1994 .