A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer

The use of VCO-based quantization within continuous-time (CT) ΣΔ analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 μm CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth while consuming 40 mW from a 1.2 V supply and occupying an active area of 640 μm × 660 μm. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which achieves first-order noise shaping of its quantization noise. The quantizer structure allows the second-order CT SA ADC topology to achieve third-order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching of the DAC elements.