Impulse Immunity of Interfaces between Intelligent Media Processors and DDR3 SDRAM Memory

Integrated Circuit (IC) immunity problems are becoming demanding challenges under the traction of Moore’s Law due to configuration complexity and vast computational resources. This paper focuses on the impulse immunity of processor chips with external Double Data Rate3 (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) in consumer electronics. Test boards complying with the IEC621324 standard and a dedicated test code were designed to complete the Electrical Fast Transient Burst (EFT) and Electrostatic Discharge (ESD) tests. The test methods and their results reflecting alterations in impulse immunity have helped to analyze other similar chips to estimate the interference of an IC by a transient event and predict to what extent the IC will survive without sustaining damages.