Non-uniform Multi-Layer IC Interconnect Transmission Line Characterization for Fast Signal Transient Simulation of High-Speed/High-Density VLSI Circuits (Special Issue on TCAD for Semiconductor Industries)

A new IC interconnect transmission line parameter determination methodology and a novel fast simulation technique for non-uniform transmission lines are presented and verified. The capacitance parameter is a strong function of a shielding effect between the layers, while silicon substrate has a substantial effect on inductance parameter. Thus, they are taken into account to determine the parameters. Then the virtual straight-line-based per unit length parameters are determined in order to perform the fast transient simulation of the non-uniform transmission lines. It was shown that not only the inductance effect due to a silicon substrate but also the shielding effect between the layers are too significant to be neglected. Further, a model order reduction technique is integrated into Berkeley SPICE in order to demonstrate that the virtual straight-linebased per-unit-length parameters can be efficiently employed for the fast transient response simulation of the complicated multilayer interconnect structures. Since the methodology is very efficient as well as accurate, it can be usefully employed for IC CAD tools of high-performance VLSI circuit design. key words: interconnects, substrate e ect, shielding e ect, sig-

[1]  C. Hu,et al.  Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation , 1998 .

[2]  H. Hasegawa,et al.  Properties of Microstrip Line on Si-SiO/sub 2/ System , 1971 .

[3]  H. A. Wheeler.  Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane , 1977 .

[4]  P. Yang,et al.  Multilevel metal capacitance models for CAD design synthesis systems , 1992, IEEE Electron Device Letters.

[5]  Albert E. Ruehli,et al.  Capacitance models for integrated circuit metallization wires , 1975 .

[6]  A. Nishiyama,et al.  Design guidelines for deep-sub-micrometer interconnections , 1990, Seventh International IEEE Conference on VLSI Multilevel Interconnection.

[7]  Keith W. Goossen,et al.  Modeling of picosecond pulse propagation in microstrip interconnections of integrated circuits , 1989 .

[8]  W. Weeks.  Calculation of Coefficients of Capacitance of Multiconductor Transmission Lines in the Presence of a Dielectric Interface , 1970 .

[9]  Lawrence T. Pileggi,et al.  The Elmore delay as a bound for RC trees with generalized input signals , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Ernest S. Kuh,et al.  Exact moment matching model of transmission lines and application to interconnect delay estimation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Lawrence T. Pileggi,et al.  Transmission line synthesis via constrained multivariable optimization , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  M. Sadiku.  Numerical Techniques in Electromagnetics , 2000 .

[13]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  W. R. Eisenstadt,et al.  High-speed VLSI interconnect modeling based on S-parameter measurements , 1993 .

[15]  Ernest S. Kuh,et al.  Transient simulation of lossy interconnects based on the recursive convolution formulation , 1992 .

[16]  J.C. Chen,et al.  An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution , 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.

[17]  T. Sarkar,et al.  Multiconductor Transmission Lines In Multilayered Dielectric Media , 1984 .