Automated integration of fault injection into the ASIC design flow

Fault injection is a widely used technique for validation of fault-tolerant mechanisms implemented in circuits and systems. Simulation-based fault injection could be used for early evaluation of the system's fault-tolerance during design. We propose a flexible procedure for automated integration of fault injection into the ASIC design flow. The gate-level netlist e.g., obtained after synthesis or layout is processed and prepared to enable injecting transients (SEUs and SETs) and permanent (stuck-at) faults. Fault injectors are automatically generated according to the user specification of the faults that are to be injected. That is, our procedure automatically creates a simulation-ready fault injection environment, given the gate-level netlist of the circuit and the fault characteristics such as type, time, probability and rate of occurrence. In order to evaluate our approach we exhaustively simulate an 8-bit ALU, showing the number of injected faults, errors and simulation times. Furthermore, we inject faults into an 8-core embedded multiprocessor with over 3.1M inverter gates. Although gate-level simulation is generally slow, the results show that our environment increases the simulation time from 1,17× to 2×, if extremely high fault rates are not specified.