Keynote: Variation-tolerant adaptive and resilient designs in nanoscale CMOS

Summary form only given, as follows. Process, voltage and temperature (PVT) variations pose major challenges to achieving energy-efficient performance in multi-core & many-core processors and SoC designs in nanoscale CMOS. Aging-induced transistor and interconnect degradations limit power and performance. Impacts of variations and aging are further aggravated in the Near-Threshold Voltage (NTV) operating regime where energy efficiency peaks. Interconnect delays are becoming bottlenecks to efficient global communications across the die. We will discuss variation-tolerant logic and memory design techniques that enable robust operation in nanoscale CMOS. We will present voltage-frequency adaptation and resiliency schemes that can mitigate impacts of dynamic variations and aging. Many-core processor designs that use a mesochronous Network-on-Chip (NoC) mesh to overcome clock distribution and global interconnect challenges will be presented. Opportunities offered by fully asynchronous designs to further improve tolerance to extreme variations will be discussed.