A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier

This paper presents a 0.5-to-1 V, 9-bit, 15-to-90 MS/s digitally interpolated pipelined-SAR ADC. The proposed digital interpolation alleviates the inter-stage gain requirement of a pipelined-SAR ADC making this ADC insensitive to gain variation. With a relaxed gain requirement, an open-loop dynamic amplifier is employed as the residue amplifier making the proposed design high-speed, clock-scalable, and robust to supply voltage scaling. The prototype ADC fabricated in 65 nm CMOS demonstrates an ENOB of 7.88 bits up to 30 MS/s with an input close to the Nyquist frequency at 0.6 V. At this conversion rate, it consumes 0.48 mW resulting in a FoM of 68 fJ/conv.-step.

[1]  Hae-Seung Lee,et al.  A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC , 2012, IEEE Journal of Solid-State Circuits.

[2]  Han Yan,et al.  11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[3]  Hyuk Sun,et al.  A 10-Bit 800-MHz 19-mW CMOS ADC , 2014, IEEE Journal of Solid-State Circuits.

[4]  Daehwa Paik,et al.  A low-noise self-calibrating dynamic comparator for high-speed ADCs , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[5]  Jan Craninckx,et al.  A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS , 2013, 2013 Symposium on VLSI Circuits.

[6]  Hsin-Shu Chen,et al.  11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[7]  Akira Matsuzawa,et al.  A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[8]  Sai-Weng Sin,et al.  Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S Pipelined-SAR ADC , 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

[9]  Chih-Cheng Hsieh,et al.  A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.