A physically based model for low-frequency noise of poly-silicon resistors

In this work an analytical first principle model for the current noise of poly-Si layers is presented and compared with measured data. For these resistors frequently used in analog CMOS applications the observed noise is much higher than predicted by the models used in circuit simulation. For the first time, dependencies on specific processing parameters such as doping or deposition techniques are investigated and explained. Moreover, deviations in the noise behavior of small size resistors are described satisfactorily. Guidelines for analog circuit design and a model suitable for circuit simulation are presented.