PHY Adapter Layer Design for Low-power fast serial bus protocol

Interface used to connect chips is the main reason of EMI problem and requires excessive space of PCB to accomodate numerous parallel lines. UniPro uses a PHY layer for fast speed of transmission. PHY layer for UniPro generally uses a protocol with fast serial interface. Various approaches are being developed to implement the PHY layer. A PHY adapter can plug various PHY layers into UniPro protocol without modifications of data link layer of UniPro. In this paper, we design a PHY adapter that consists of power management unit and Rx/Tx buffers. The PHY adapter converts data from 2 pairs of data lane of PHY to 17-bit packet for upper layer. The PHY adapter is design in Verilog HDL and verified using ActiveHDL. The synthesis result shows that the gate count is 2,150 and the operation frequency is 199㎒.