CRUSADE: hardware/software co-synthesis of dynamically reconfigurable heterogeneous real-time distributed embedded systems

Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-time reconfigurable hardware components such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). In this paper, we address the problem of hardware/ software co-synthesis of dynamically reconfigurable embedded systems. Our co-synthesis system, CRUSADE, takes as an input embedded system specifications in terms periodic acyclic task graphs with rate constraints and generates dynamically reconfigurable heterogeneous distributed hardware and software architecture meeting real-time constraints while minimizing the system hardware cost. We identify the group of tasks for dynamic reconfiguration of programmable devices and synthesize an efficient programming interface for reconfiguring reprogrammable devices. Real-time systems require that the execution time for tasks mapped to reprogrammable devices are managed effectively such that real-time deadlines are not exceeded. To address this, we propose a technique to effectively manage delay in reconfigurable devices. Our approach guarantees that the real-time task deadlines are always met. To the best of our knowledge, this is the first co-synthesis algorithm which targets dynamically reconfigurable embedded systems. We also show how our co-synthesis algorithm can be easily extended to consider fault-detection and fault-tolerance. Application of CRUSADE and its fault tolerance extension, CRUSADE-FT to several real-life large examples (up to 7400 tasks) from mobile communication network base station, video distribution router, a multi-media system, and synchronous optical network (SONET) and asynchronous transfer mode (ATM) based telecom systems shows that up to 56% system cost savings can be realized.

[1]  Edward A. Lee,et al.  The extended partitioning problem: hardware/software mapping and implementation-bin selection , 1995, Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype.

[2]  Luciano Lavagno,et al.  Hardware-Software Co-Design of Embedded Systems , 1997 .

[3]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[4]  Niraj K. Jha,et al.  COFTA: hardware-software co-synthesis of heterogeneous distributed embedded system architectures for low overhead fault tolerance , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[5]  Hugo De Man,et al.  CoWare—A design environment for heterogeneous hardware/software systems , 1996, EURO-DAC '96/EURO-VHDL '96.

[6]  Mark Shand,et al.  Programmable active memories: reconfigurable systems come of age , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Frank Vahid,et al.  SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Klaus Buchenrieder,et al.  A prototyping environment for control-oriented HW/SW systems using state-charts, activity-charts and FPGA's , 1994, EURO-DAC '94.

[9]  Alice C. Parker,et al.  SOS: Synthesis of application-specific heterogeneous multiprocessor systems , 2001, J. Parallel Distributed Comput..

[10]  P. A. Subrahmanyam,et al.  Hardware/software partitioning for multi-function systems , 1997, ICCAD 1997.

[11]  Miodrag Potkonjak,et al.  System-level synthesis of low-power hard real-time systems , 1997, DAC.

[12]  Frank Vahid,et al.  Incremental hardware estimation during hardware/software functional partitioning , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Niraj K. Jha,et al.  COSYN: hardware-software co-synthesis of embedded systems , 1997, DAC.

[14]  Wayne Wolf,et al.  Communication synthesis for distributed embedded systems , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[15]  Jörg Henkel,et al.  A hardware/software partitioner using a dynamically determined granularity , 1997, DAC.

[16]  Mani B. Srivastava,et al.  SIERA: a unified framework for rapid-prototyping of system-level hardware and software , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Brad L. Hutchings,et al.  Implementation Approaches for Reconfigurable Logic Applications , 1995, FPL.

[18]  Edward A. Lee,et al.  The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling, and Implementation-bin Selection , 1997, Des. Autom. Embed. Syst..

[19]  Edward A. Lee,et al.  Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems , 2001, Int. J. Comput. Simul..