BddCut: Towards Scalable Symbolic Cut Enumeration

While the covering algorithm has been perfected recently by the iterative approaches, such as DAOmap and IMap, its application has been limited to technology mapping. The main factor preventing the covering problem's migration to other logic transformations, such as elimination and resynthesis region identification found in SIS and FBDD, is the exponential number of alternative cuts that have to be evaluated. Traditional methods of cut generation do not scale beyond a cut size of 6. In this paper, a symbolic method that can enumerate all cuts is proposed without any pruning, up to a cut size of 10. We show that it can outperform traditional methods by an order of magnitude and, as a result, scales to 100K gate benchmarks. As a practical driver, the covering problem applied to elimination is shown where it can not only produce competitive area, but also provide more than 6times average runtime reduction of the total runtime in FBDD, a BDD based logic synthesis tool with a reported order of magnitude faster runtime than SIS and commercial tools with negligible impact on area.

[1]  Jianwen Zhu,et al.  FBDD: a folded logic synthesis system , 2005, 2005 6th International Conference on ASIC.

[2]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Jason Cong,et al.  DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs , 2004, ICCAD 2004.

[4]  Russell Tessier,et al.  BDD-based logic synthesis for LUT-based FPGAs , 2002, TODE.

[5]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[6]  M. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2000, Proceedings 37th Design Automation Conference.

[7]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[8]  Stephen Dean Brown,et al.  Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Jason Cong,et al.  Cut ranking and pruning: enabling a general and efficient FPGA mapping solution , 1999, FPGA '99.

[10]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[11]  Robert K. Brayton,et al.  Improvements to Technology Mapping for LUT-Based FPGAs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[13]  Fabio Somenzi,et al.  CUDD: CU Decision Diagram Package Release 2.2.0 , 1998 .

[14]  Jason Cong,et al.  Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[15]  F. Somenzi Binary Decision Diagrams , 1999 .

[16]  Jason Cong,et al.  On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping , 1993, 30th ACM/IEEE Design Automation Conference.