Soft error considerations for deep-submicron CMOS circuit applications
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N. Cohen | T. Sriram | N. Leland | D. Moyer | S. Butler | R. Flatley | Neil Cohen | Sriram | David Moyer | Steve Butler
[1] C. Lage,et al. Soft error rate and stored charge requirements in advanced high-density SRAMs , 1993, Proceedings of IEEE International Electron Devices Meeting.
[2] G. R. Srinivasan,et al. Soft-error Monte Carlo modeling program, SEMM , 1996, IBM J. Res. Dev..
[3] B. Davari. CMOS technology scaling, 0.1 /spl mu/m and beyond , 1996, International Electron Devices Meeting. Technical Digest.
[4] James L. Walsh,et al. IBM experiments in soft fails in computer electronics (1978-1994) , 1996, IBM J. Res. Dev..
[5] Yoshiharu Tosaka,et al. Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits , 1998 .