Low Thermal Resistance (0.5 K/W) Ga₂O₃ Schottky Rectifiers With Double-Side Packaging

The low thermal conductivity of Ga<sub>2</sub>O<sub>3</sub> has arguably been the most serious concern for Ga<sub>2</sub>O<sub>3</sub> power and RF devices. Despite many simulation studies, there is no experimental report on the thermal resistance of a large-area, packaged Ga<sub>2</sub>O<sub>3</sub> device. This work fills this gap by demonstrating a 15-A double-side packaged Ga<sub>2</sub>O<sub>3</sub> Schottky barrier diode (SBD) and measuring its junction-to-case thermal resistance (<inline-formula> <tex-math notation="LaTeX">${R}_{\theta {\mathrm {JC}}}$ </tex-math></inline-formula>) in the bottom-side- and junction-side-cooling configurations. The <inline-formula> <tex-math notation="LaTeX">${R}_{\theta \mathrm{JC}}$ </tex-math></inline-formula> characterization is based on the transient dual interface method, i.e., JEDEC 51-14 standard. The <inline-formula> <tex-math notation="LaTeX">${R}_{\theta \mathrm{JC}}$ </tex-math></inline-formula> of the junction- and bottom-cooled Ga<sub>2</sub>O<sub>3</sub> SBD was measured to be 0.5 K/W and 1.43 K/W, respectively, with the former <inline-formula> <tex-math notation="LaTeX">${R}_{\theta \mathrm{JC}}$ </tex-math></inline-formula> lower than that of similarly-rated commercial SiC SBDs. This low <inline-formula> <tex-math notation="LaTeX">${R}_{\theta \mathrm{JC}}$ </tex-math></inline-formula> is attributable to the heat extraction directly from the Schottky junction instead of through the Ga<sub>2</sub>O<sub>3</sub> chip. The <inline-formula> <tex-math notation="LaTeX">${R}_{\theta \mathrm{JC}}$ </tex-math></inline-formula> lower than that of commercial SiC devices proves the viability of Ga<sub>2</sub>O<sub>3</sub> devices for high-power applications and manifest the significance of proper packaging for their thermal management.