Analysis of a novel stage configurable ROPUF design

Silicon based Physical Unclonable Function (SPUF), a chip level identifier that utilizes the inherent irregular manufacturing process variations, can be extended to Ring Oscillator PUFs (ROPUFs). The ROPUF structure, although promising for FPGA based platforms, is not area efficient in terms of response bit per RO circuit implementation. This paper introduces an area efficient Stage Configurable ROPUF (SCROPUF) design based on XOR gates and a functional block which significantly increases the output frequency comparison pairs. The design is implemented on six Xilinx Artix-7 FPGAs. In this work, the output frequency data from 125 SCROs is evaluated with regard to the following quality factors: uniqueness, uniformity, and bit-aliasing along with the NIST statistical tests for randomness. Also, the average static intra-chip variation is shown to be higher than the noise component signifying higher reliability of the design.

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