Improved fault emulation for synchronous sequential circuits

Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated to fault emulation for sequential circuits are explained and alternative implementations are discussed. An environment for hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40 to 500 times as compared to the state-of-the-art in fault simulation. Average speedup provided by the method is 250 that is about an order of magnitude higher than previously cited in the literature. Based on the experiments, we can conclude that it is beneficial to use emulation when large numbers of test vectors is required.

[1]  Richard W. Wieler,et al.  Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator , 1994, FPL.

[2]  Miron Abramovici,et al.  Fault simulation on reconfigurable hardware , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[3]  Raimund Ubar,et al.  Turbo Tester: A CAD System for Teaching Digital Test , 1998 .

[4]  Alexander Saldanha,et al.  Fast discrete function evaluation using decision diagrams , 1995, ICCAD.

[5]  Shi-Yu Huang,et al.  Fault emulation: a new approach to fault grading , 1995, ICCAD.

[6]  A.L. Sangiovanni-Vincentelli,et al.  Fast discrete function evaluation using decision diagrams , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[7]  Jaan Raik,et al.  Fault Emulation on FPGA: A Feasibility Study , 2003 .

[8]  Sergio D'Angelo,et al.  A fault injection tool for SRAM-based FPGAs , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[9]  Luc Burgun,et al.  Serial fault emulation , 1996, DAC '96.

[10]  Jaan Raik,et al.  Evaluating Fault Emulation on FPGA , 2004, FPL.

[11]  Cheng-Wen Wu,et al.  Sequential circuit fault simulation using logic emulation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Shyue-Kung Lu,et al.  Combinational circuit fault diagnosis using logic emulation , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[13]  Janak H. Patel,et al.  Proofs: a fast, memory efficient sequential circuit fault simulator , 1991, DAC '90.

[14]  Richard W. Wieler,et al.  Emulating static faults using a Xilinx based emulator , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[15]  Erich Barke,et al.  A new approach to fault emulation , 1997, Proceedings 8th IEEE International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype.

[16]  Dhiraj K. Pradhan,et al.  EBIST: a novel test generator with built-in fault detection capability , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.