Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems

System optimization techniques are widely used to improve energy efficiency as well as overall performance. Dynamic voltage scaling (DVS) is acknowledged to be successful in reducing processor energy consumption. Due to the increasing significance of the memory subsystem’s energy consumption, dynamic cache reconfiguration (DCR) techniques are recently proposed at the aim of saving cache subsystem’s energy con- sumption. As the manufacturing technology scales into the order of nanometers, leakage current, both in the processor and cache subsystem, becomes a significant contributor in the overall power dissipation. In this paper, we efficiently integrate processor voltage scaling and cache reconfiguration together that is aware of leakage power to minimize overall system energy consumption. Experimental results demonstrate that our approach outperforms existing techniques by on average 12 - 23%.

[1]  G. Sohi,et al.  A static power model for architects , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.

[2]  Rajesh K. Gupta,et al.  Energy-aware task scheduling with task synchronization for embedded real-time systems , 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Gang Qu,et al.  Temperature-Aware Leakage Minimization Technique for Real-Time Systems , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[4]  Yann-Hang Lee,et al.  Scheduling techniques for reducing leakage power in hard real-time systems , 2003, 15th Euromicro Conference on Real-Time Systems, 2003. Proceedings..

[5]  Bill Moyer,et al.  A low power unified cache architecture providing power and performance flexibility , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[6]  Weixun Wang,et al.  Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[7]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[8]  Trevor Mudge,et al.  Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[9]  Jane W.-S. Liu.  Real-Time Systems , 2000, Encyclopedia of Algorithms.

[10]  Frank Vahid,et al.  A Self-Tuning Configurable Cache , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[11]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[12]  Hamid Noori,et al.  The effect of temperature on cache size tuning for low energy embedded systems , 2007, GLSVLSI '07.

[13]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[14]  Doug Burger,et al.  Evaluating Future Microprocessors: the SimpleScalar Tool Set , 1996 .

[15]  Miodrag Potkonjak,et al.  Power optimization of variable-voltage core-based systems , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Karam S. Chatha,et al.  Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[17]  André C. Nácul,et al.  Dynamic voltage and cache reconfiguration for low power , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[18]  David H. Albonesi,et al.  Selective cache ways: on-demand cache resource allocation , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[19]  Tei-Wei Kuo,et al.  Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor , 2006, LCTES '06.

[20]  Rajesh K. Gupta,et al.  Leakage aware dynamic voltage scaling for real-time embedded systems , 2004, Proceedings. 41st Design Automation Conference, 2004..

[21]  Jian-Jia Chen,et al.  Cache leakage control mechanism for hard real-time systems , 2007, CASES '07.

[22]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[23]  Frank Vahid,et al.  A highly configurable cache for low energy embedded systems , 2005, TECS.

[24]  Kaushik Roy,et al.  Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories , 2000, ISLPED '00.

[25]  Giorgio C. Buttazzo,et al.  HARD REAL-TIME COMPUTING SYSTEMS Predictable Scheduling Algorithms and Applications , 2007 .

[26]  Rami G. Melhem,et al.  Dynamic and aggressive scheduling techniques for power-aware real-time systems , 2001, Proceedings 22nd IEEE Real-Time Systems Symposium (RTSS 2001) (Cat. No.01PR1420).

[27]  Tei-Wei Kuo,et al.  Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems. , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[28]  Ann Gordon-Ross,et al.  SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems , 2009, 2009 22nd International Conference on VLSI Design.

[29]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[30]  Trevor Mudge,et al.  Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.

[31]  Chong-Min Kyung,et al.  Task partitioning algorithm for intra-task dynamic voltage scaling , 2008, 2008 IEEE International Symposium on Circuits and Systems.