Novel Bitcells for Scaled CMOS Nodes and Soft Error Tolerance

This chapter presents novel GC-eDRAM bitcells specifically designed and optimized for the most advanced CMOS nodes, as well as for soft error tolerance which becomes an increasingly important issue with technology scaling. A novel 4-transistor (4T) GC with selective internal feedback to protect only the weaker data level among “0” and “1” is presented. A simulation based proof of concept is provided for a 65 nm CMOS node. A redundant 4T GC bitcell for soft error tolerance is presented next. This 4T GC offers per-cell redundancy at a small area cost and enables GC-eDRAM array architectures with a parity column for error correction.

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