ONOFIC approach: low power high speed nanoscale VLSI circuits design

Shrinking in the device dimensions increases the device density on the chip and thus reducing the overall chip area requirement for logic implementation. Minimising the chip area is not a lonely optimisation performance factor for a VLSI chip designer. The other equally important performance parameters such that power dissipation and propagation delay are the thinkable facts for a designer. The focusable part of power dissipation is the huge leakage current in deep submicron (DSM) regime. Many leakage reduction techniques are applied to reduce the leakage current in the DSM regime but they have own limitations. Our proposed on/off logic (ONOFIC) approach gives an excellent settlement between power dissipation and propagation delay for designing the nanoscale CMOS circuits. It uses extra insertion of two transistors (an NMOS and a PMOS) within the logic block. The exact on/off level of the ONOFIC block improves the power dissipation and propagation delay of the logic circuits. In this article, ONOFIC approach is compared with the LECTOR leakage reduction technique and output results show that our proposed approach significantly reduces the power dissipation and enhancing the speed of the logic circuits with superior power-delay product.