Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA
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[1] Marco Platzner,et al. Virtualization of Hardware - Introduction and Survey , 2004, ERSA.
[2] Guy Lemieux,et al. ZUMA: An Open FPGA Overlay Architecture , 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.
[3] Frank Vahid,et al. Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only) , 2005, FPGA '05.
[4] Moritoshi Yasunaga,et al. Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).
[5] Marco Platzner,et al. ReconOS: Multithreaded programming for reconfigurable computers , 2009, TECS.
[6] Kenneth B. Kent,et al. The VTR project: architecture and CAD for FPGAs from verilog to routing , 2012, FPGA '12.
[7] Gordon J. Brebner,et al. The swappable logic unit: a paradigm for virtual hardware , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[8] Jürgen Becker,et al. A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.
[9] Dominique Lavenier,et al. Placing, Routing, and Editing Virtual FPGAs , 2001, FPL.
[10] Marco Platzner,et al. ReconOS: An Operating System Approach for Reconfigurable Computing , 2014, IEEE Micro.
[11] Vincenzo Piuri,et al. Virtual FPGAs: Some Steps Behind the Physical Barriers , 1998, IPPS/SPDP Workshops.
[12] Hugo De Man,et al. A hardware virtual machine for networked reconfiguration , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).
[13] James Coole,et al. Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing , 2010, 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[14] Lukás Sekanina. Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware , 2003, ICES.