Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays (FPGAs), thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array (FPGA) electronic design automation (EDA) tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.
[1]
Shih-Chieh Chang,et al.
A vectorless estimation of maximum instantaneous current for sequential circuits
,
2004,
ICCAD 2004.
[2]
Sandeep K. Shukla,et al.
Power estimation methodology for a high-level synthesis framework
,
2009,
2009 10th International Symposium on Quality Electronic Design.
[3]
Stephen Dean Brown,et al.
Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits
,
2010,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4]
Jason Cong,et al.
Power modeling and characteristics of field programmable gate arrays
,
2005,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.