A study of digital decoders in flash analog-to-digital converters

Digital decoders in flash analog-to-digital converters are studied. An attractive approach for realizing the decoder is to count the ones in the thermometer coded comparator output with, e.g. a Wallace tree. Such an ones-counter can be fast and it incorporates global bubble error correction. We also suggest an improvement of the Wallace tree decoder, obtained by applying folding. This yields a decoder with less area and a circuit with shorter critical path, which should make it possible to design for lower power consumption than the Wallace tree decoder. The folded decoder also enables introduction of extra error correction circuitry for the same hardware cost, or less, as for the Wallace tree decoder, which does not have the extra bubble error correction. This makes the folded decoder not only attractive, but also to applications where low bit error rate is crucial.

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