An 8-bit 1-GS/s flash-assisted time-interleaved SAR ADC

This paper presents an 8-bit 1GS/s flash-assisted time-interleaved SAR ADC consisting of one 2-bit flash ADC and one 6-bit SAR ADC with 4 time-interleaved channels. The hybrid capacitive DAC controls segmented thermometer MSB capacitors and the binary LSBs. This architecture improves speed significantly with 1GHz sampling rates. This work realizes the ENOB with 7.93-bit, consumes power of 4.86 mW from a 1.2-V supply voltage in 65-nm process and achieves FoMs to 19.9 and 24.7 fJ/conversion-step at low and nyquist input, respectively.

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[2]  Michael P. Flynn,et al.  A SAR-Assisted Two-Stage Pipeline ADC , 2011, IEEE Journal of Solid-State Circuits.