Characteristics and scaling properties of n-p-n transistors with a sidewall base contact structure

Symmetrical n-p-n transistors with a sidewall base contact structure (SICOS) are developed and high cutoff frequency of 14 GHz in downward operation and 4 GHz in upward operation were obtained with a small transistor area of 145 µm2for a 3 µm × 4 µm emitter size. This excellent performance is the direct result of the extreme reduction of parasitic regions. Scaling laws of device characteristics are discussed. It is shown that the current gain and transconductance will be lowered in scaled down transistors. Regarding other properties, upward characteristics will be improved more than downward characteristics.

[1]  H. C. de Graaff,et al.  Measurements of bandgap narrowing in Si bipolar transistors , 1976 .

[2]  Hiroaki Nakamura,et al.  Bipolar Technologies for High Speed VLSIs , 1981, 1981 Symposium on VLSI Technology. Digest of Technical Papers.

[3]  H. C. Poon,et al.  High injection in epitaxial transistors , 1969 .

[4]  P. Ashburn,et al.  The influence of surface treatments on the electrical characteristics of polysilicon emitter bipolar transistors , 1982, 1982 International Electron Devices Meeting.

[5]  D.D. Tang,et al.  A symmetrical bipolar structure , 1980, 1980 International Electron Devices Meeting.

[6]  Tak H. Ning The Potential of Bipolar Devices for VLSI , 1981, 1981 Symposium on VLSI Technology. Digest of Technical Papers.

[7]  T. Nakamura,et al.  Hole-spreading effect on upward current gain in n-p-n transistors , 1985, IEEE Transactions on Electron Devices.

[8]  C. T. Kirk,et al.  A theory of transistor cutoff frequency (fT) falloff at high current densities , 1962, IRE Transactions on Electron Devices.

[9]  W.C. Ko,et al.  Current gain in polysilicon emitter transistors , 1983, IEEE Transactions on Electron Devices.

[10]  N. Hanaoka,et al.  Perspective of scaled bipolar devices , 1981, 1981 International Electron Devices Meeting.

[11]  M. Nagata,et al.  Self-aligned transistor with sidewall base electrode , 1982, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[12]  P. M. Solomon,et al.  Bipolar transistor design for optimized power-delay logic circuits , 1979 .

[13]  F. Klaassen Device physics of integrated injection logic , 1975, IEEE Transactions on Electron Devices.

[14]  H. C. Poon,et al.  An integral charge control model of bipolar transistors , 1970, Bell Syst. Tech. J..

[15]  D.D. Tang,et al.  Method for determining the emitter and base series resistances of bipolar transistors , 1984, IEEE Transactions on Electron Devices.