Design and IC Implementation of High Efficiency and Low Power DC-DC Converter

A design method of a high-efficiency,low-power DC-DC converter with pulse-width modulation(PWM) and pulse-frequency modulation(PFM) modes is presented in the paper.The converter operates in PWM mode at a switching frequency of 1 MHz when the load current is larger than 60 mA,and works in PFM mode with a reduced switching frequency if the load current is less than 60 mA,ensuring highly efficient operation within a large range(0~250 mA) of load current variation.As the output voltage reaches 102 % of the anticipated output value,the converter enters sleep mode,during which the quiescent current decreases.The chip was implemented using CSMC 0.5 μm CMOS mixed-signal process.The experimental results indicate that the converter operates in PWM/PFM modes and performs seamless switching between them,displaying good load/line regulation.The output voltage error is less than ±2 %,the maximum quiescent current less than 15 μA and the maximum of efficiency up to 92.6 %.