An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution because their repetitive structure matches the data-parallel execution pattern inherent in pixel-type processing. But the lack of support for communicating pixel data over variable distances has forced designers to allocate dedicated hardware or FPGAs for compensating lens distortion and other non-linear operations. We propose a hardware extension to SIMD processors that enables dynamic communication. Using detailed area cost models and a high-level simulator we optimize the extension with regard to the number of buses, bus arbitration policies, and local instruction buffer sizes
[1]
H SzymanskiTed,et al.
Power complexity of multiplexer-based optoelectronic crossbar switches
,
2005
.
[2]
K. Soumyanath,et al.
Sub-500 ps 64 b ALUs in 0.18 /spl mu/m SOI/bulk CMOS: Design & scaling trends
,
2001,
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[3]
Henk Corporaal,et al.
Smartcam Design Framework.
,
2003
.
[4]
K. Soumyanath,et al.
Sub-500-ps 64-b ALUs in 0 . 18-m SOI / Bulk CMOS : Design and Scaling Trends
,
2001
.
[5]
Henk Corporaal,et al.
Real-Time Face Recognition on a Smart Camera.
,
2003
.