Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM

IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout

[1]  Jacek M. Zurada,et al.  Dynamic noise margins of MOS logic gates , 1989, IEEE International Symposium on Circuits and Systems,.

[2]  Louise Trevillyan,et al.  EDA in IBM: past, present, and future , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Vasant B. Rao,et al.  Aggressive crunching of extracted RC netlists , 2002, TAU '02.

[4]  Norman P. Jouppi Derivation of Signal Flow Direction in MOS VLSI , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  David Blaauw,et al.  Statistical gate delay model considering multiple input switching , 2004, Proceedings. 41st Design Automation Conference, 2004..

[6]  Carl Ebeling,et al.  SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[7]  Kenneth L. Shepard,et al.  Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors , 1997, IBM J. Res. Dev..

[8]  Kenneth L. Shepard,et al.  Noise in deep submicron digital design , 1996, Proceedings of International Conference on Computer Aided Design.

[9]  J. Petrovick,et al.  The circuit and physical design of the POWER4 microprocessor , 2002, IBM J. Res. Dev..

[10]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Malgorzata Marek-Sadowska,et al.  Crosstalk reduction for VLSI , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  K. L. Shepard,et al.  Noise in deep submicron digital design , 1996, ICCAD 1996.

[13]  Kenneth L. Shepard,et al.  Harmony: static noise analysis of deep submicron digital integrated circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Melvin A. Breuer,et al.  A new gate delay model for simultaneous switching and its applications , 2001, DAC '01.

[15]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluator , 1991, 28th ACM/IEEE Design Automation Conference.

[16]  Kenneth L. Shepard,et al.  Conquering Noise in Deep-Submicron Digital ICs , 1998, IEEE Des. Test Comput..

[17]  Ronald A. Rohrer,et al.  Adaptively controlled explicit simulation , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Ronald A. Rohrer,et al.  Piecewise approximate circuit simulation , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluation using AWE , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..