A novel structure for tunable complex-arithmetic heterodyne filters

The standard approach to designing a tunable complex heterodyne filter is to take a high-pass (or low-pass) digital filter and rotate it by multiplying by a complex exponential. This is a three heterodyne process that rotates the filter first to the left, then two to the right, and finally back to the left. An alternative is to use a complex digital filter to eliminate the frequencies in the bottom half of the unit circle such that a two heterodyne process can be used. The advantage of the two heterodyne process is not only the elimination of one heterodyne operation, but also a reduction in hardware due to the need to only calculate the real output of the last heterodyne stage.

[1]  Michael A. Soderstrand,et al.  Adaptive filtering using heterodyne frequency translation , 1997, Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg.

[2]  M.A. Soderstrand,et al.  Implementation of a tunable heterodyne notch filter , 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).

[3]  Michael A. Soderstrand CSD multipliers for FPGA DSP applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[4]  M.A. Soderstrand,et al.  FPGA implementation of adaptive heterodyne filters , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[5]  Sanjay Sharma,et al.  A Tunable Heterodyne Filter Design On Reconfigurable Fabric , 2004, J. Circuits Syst. Comput..

[6]  M.A. Soderstrand,et al.  Comparison of two techniques for attenuation of narrow-band interference in spread-spectrum communication systems , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[7]  Michael M. Goodwin,et al.  The STFT, Sinusoidal Models, and Speech Modification , 2008 .

[8]  Gary E. Ford,et al.  Efficient pipelined tunable heterodyne notch filter implementation in FPGAs , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[9]  Shintaro Izumi,et al.  A single-chip sensor node LSI with synchronous MAC protocol and divided data-buffer SRAM , 2009, 2009 International SoC Design Conference (ISOCC).

[10]  Michael A. Soderstrand,et al.  FPGA implementation of a tunable band-pass filter using the "basic heterodyne block" , 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

[11]  Michael A. Soderstrand,et al.  Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[12]  Michael A. Soderstrand,et al.  Full tunable digital heterodyne IIR filters , 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

[13]  Michael A. Soderstrand,et al.  Adaptive heterodyne filters (AHF) for detection and attenuation of narrow band signals , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

[14]  Adaptive Notch Filters Using A Complex Heterodyne Approach , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

[15]  Makoto Nagata,et al.  On-chip power noise measurements of high-frequency CMOS digital circuits , 2009, 2009 International SoC Design Conference (ISOCC).