Interference-Aware Memory Allocation for Real-Time Multi-Core Systems

Computing tight upper bounds for the Worst-Case Execution Time (WCET) at design-time is a crucial step when developing hard real-time software. For multi-core processors, however, timing interference between processor cores is a major problem, which may lead to overestimated WCET bounds. This work investigates possible solutions to reduce interference costs using synchronization-based interference models and appropriate memory allocation schemes. An interference-aware Integer Linear Programming (ILP) formulation of the memory allocation problem is presented to optimally map the variables of parallel programs to a set of distributed memory segments. The approach uses a generic model of the hardware platform, such that it applies to a wide range of multi-core targets, including complex Network-on-Chip (NoC) interconnects. A case study with six different platform configurations shows that interference costs can be bounded more tightly using the proposed interference model. An evaluation of the allocation scheme furthermore shows that the optimization approach can reduce interference costs by up to 49%.