Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs

Hole mobility and velocity are extracted from scaled strained-Si0.45Ge0.55 channel p-MOSFETs on insulator. Devices have been fabricated with sub-100-nm gate lengths, demonstrating hole mobility and velocity enhancements in strained- Si0.45Ge0.55 channel devices relative to Si. The effective hole mobility is extracted utilizing the dR/dL method. A hole mobility enhancement is observed relative to Si hole universal mobility for short-channel devices with gate lengths ranging from 65 to 150 nm. Hole velocities extracted using several different methods are compared. The hole velocity of strained-SiGe p-MOSFETs is enhanced over comparable Si control devices. The hole velocity enhancements extracted are on the order of 30%. Ballistic velocity simulations suggest that the addition of (110) uniaxial compressive strain to Si0.45Ge0.55 can result in a more substantial increase in velocity relative to relaxed Si.

[1]  Hole mobility enhancement and Si cap optimization in nanoscale strained Si1-xGex PMOSFETs , 2004 .

[2]  O. Faynot,et al.  Co-integrated dual strained channels on fully depleted sSDOI CMOSFETs with HfO/sub 2//TiN gate stack down to 15nm gate length , 2005, 2005 IEEE International SOI Conference Proceedings.

[3]  S. Chou,et al.  Relationship between measured and intrinsic transconductances of FET's , 1987, IEEE Transactions on Electron Devices.

[4]  Supika Mashiro,et al.  Enhanced performance in sub-100 nm CMOSFETs using strained epitaxial silicon-germanium , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[5]  P. Bai,et al.  A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[6]  G.J. Hu,et al.  Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's , 1987, IEEE Transactions on Electron Devices.

[7]  S. Narasimha,et al.  Hole Transport in Nanoscale p-type MOSFET SOI Devices with High Strain , 2007, 2007 65th Annual Device Research Conference.

[8]  N. Cherkashin,et al.  Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[9]  L. T. Su,et al.  A study of deep-submicron MOSFET scaling based on experiment and simulation , 1995 .

[10]  M. Heyns,et al.  High-Performance Deep Submicron Ge pMOSFETs With Halo Implants , 2007, IEEE Transactions on Electron Devices.

[11]  A. Majumdar,et al.  Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs , 2008, IEEE Electron Device Letters.

[12]  A. Khakifirooz,et al.  MOSFET performance scaling: Limitations and future options , 2008, 2008 IEEE International Electron Devices Meeting.

[13]  L. Selmi,et al.  Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application , 2001 .

[14]  D. Antoniadis,et al.  On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit? , 2001, IEEE Electron Device Letters.

[15]  M. Lee,et al.  Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors , 2005 .

[16]  Mark S. Lundstrom.  Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.

[17]  M. Uchida,et al.  Performance Enhancement of pMOSFETs Depending on Strain, Channel Direction, and Material , 2005, 2005 International Conference On Simulation of Semiconductor Processes and Devices.

[18]  S. Narasimha,et al.  Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[19]  D.A. Antoniadis,et al.  Transistor Performance Scaling: The Role of Virtual Source Velocity and Its Mobility Dependence , 2006, 2006 International Electron Devices Meeting.

[20]  J. Hoyt,et al.  Super critical thickness SiGe-channel heterostructure p-type metal-oxide-semiconductor field-effect transistors using laser spike annealing , 2008 .

[21]  K. Suzuki,et al.  High Performance 60 nm Gate Length Germanium p-MOSFETs with Ni Germanide Metal Source/Drain , 2007, 2007 IEEE International Electron Devices Meeting.

[22]  K. Saraswat,et al.  Low defect ultra-thin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT) , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[23]  S. Laux,et al.  Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys , 1996 .

[24]  M. Jurczak,et al.  Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..