Cell flipping in VLSI design is an operation in which some of the cells are replaced with their ``mirror images'''' with respect to a vertical axis, while keeping them in the same slot. After the placement of all the cells, one can apply cell flipping in order to further decrease the total area, approximating this objective by minimizing total wire length, channel width, etc. However, finding an optimal set of cells to be flipped is usually a difficult problem. In this paper we show that cell flipping can be efficiently applied to minimize channel density in the standard cell technology. We show that an optimal flipping pattern can be found in $O(p(\frac{n}{c})^{c})$ time, where $n$, $p$ and $c$ denote the number of nets, pins and channels, respectively. Moreover, in the one channel case (i.e. when $c=1$) the cell flipping problem can be solved in $O(p\log n)$ time. For the multi-channel case we present both an exact enumeration scheme and a mixed-integer program that generates an approximate solution very quickly. We present computational results on examples up to 139 channels and 65 000 cells.
[1]
Ting-Chi Wang,et al.
Performance-driven channel pin assignment algorithms
,
1995,
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2]
C. Lekkeikerker,et al.
Representation of a finite graph by a set of intervals on the real line
,
1962
.
[3]
Chung-Kuan Cheng,et al.
The Orientation of Modules Based on Graph Decomposition
,
1991,
IEEE Trans. Computers.
[4]
Pierre Hansen,et al.
Roof duality, complementation and persistency in quadratic 0–1 optimization
,
1984,
Math. Program..
[5]
A. S. LaPaugh,et al.
ALGORITHMS FOR INTEGRATED CIRCUIT LAYOUT: AN ANALYTIC APPROACH
,
1980
.
[6]
Robert E. Tarjan,et al.
A Linear-Time Algorithm for Testing the Truth of Certain Quantified Boolean Formulas
,
1979,
Inf. Process. Lett..
[7]
Thomas Lengauer,et al.
Combinatorial algorithms for integrated circuit layout
,
1990,
Applicable theory in computer science.