A 30 Year Retrospective on Dennard's MOSFET Scaling Paper

The MOSFET scaling principles for obtaining simultaneous improvements in transistor density, switching speed, and power dissipation described by Robert H. Dennard and others in "Design of Ion-implanted MOSFETs with Very Small Physical Dimensions" (1974 ) became a roadmap for the semiconductor industry to provide systematic and predictable transistor improvements. New technology generations emerging approximately every three years during the 1970's and 1980's and appearing every other year starting in the mid-1990's, promise to continue although we face growing challenges.

[1]  Yuan Taur,et al.  CMOS devices below 0.1 /spl mu/m: how high will performance go? , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[2]  Robert H. Dennard,et al.  Design of ion-implanted MOSFET's with very small physical dimensions , 2007 .

[3]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[4]  C. Auth,et al.  Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[5]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[6]  P. Bai,et al.  A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..