Flexible rerouting schemes for reconfiguration of multiprocessor arrays

Abstract In a multiprocessor array, some processing elements (PEs) fail to function normally due to hardware defects or soft faults caused by overheating, overload or occupancy by other running applications. Fault-tolerant reconfiguration reorganizes fault-free PEs to a new regular topology by changing the interconnection among PEs. This paper investigates the problem of constructing as large as possible logical array with short interconnects from a physical array with faults. A flexible rerouting scheme is developed to improve the efficiency of utilizing fault-free PEs. Under the scheme, two efficient reconfiguration algorithms are proposed. The first algorithm is able to generate the maximum logical array (MLA) in linear time. The second algorithm reduces the interconnect length of the MLA, and it is capable of producing nearly optimal logical arrays in comparison to the lower bound of the interconnect length, that is also proposed in this paper. Experimental results validate the efficiency of the flexible rerouting schemes and the proposed algorithms. For 128×128 host arrays with 30% unavailable PEs, the proposed approaches improve existing algorithm up to 44% in terms of logical array size, while reducing the interconnection redundancy by 49.6%. In addition, the proposed algorithms are more scalable than existing approaches. On host arrays with 50% unavailable PEs, our algorithms can produce logical arrays with harvest over 56% while existing approaches fail to construct a feasible logical array.

[1]  Wu Jigang,et al.  Efficient reconfiguration algorithms for communication-aware three-dimensional processor arrays , 2013, Parallel Comput..

[2]  Hamid Sarbazi-Azad,et al.  Power-aware mapping for reconfigurable NoC architectures , 2007, 2007 25th International Conference on Computer Design.

[3]  Itsuo Takanami.  Self-Reconfiguring of 1½-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit , 2004, IEICE Trans. Inf. Syst..

[4]  Wen-Chung Shen,et al.  Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems , 2009, 2009 International Symposium on VLSI Design, Automation and Test.

[5]  Shambhu J. Upadhyaya,et al.  A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors , 1997, IEEE Trans. Computers.

[6]  Wu Jigang,et al.  Efficient reconfigurable techniques for VLSI arrays with 6-port switches , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Wu Jigang,et al.  Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches , 2007, IEEE Transactions on Computers.

[8]  Shantanu Dutt,et al.  Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays , 2001, J. Parallel Distributed Comput..

[9]  Hamid Sarbazi-Azad,et al.  An efficient dynamically reconfigurable on-chip network architecture , 2010, Design Automation Conference.

[10]  Hamid Sarbazi-Azad,et al.  Application-Aware Topology Reconfiguration for On-Chip Networks , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Jacques Henri Collet,et al.  Comparison of fault-tolerance techniques for massively defective fine- and coarse-grained nanochips , 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

[12]  M. Hatzimihail,et al.  A methodology for detecting performance faults in microprocessors via performance monitoring hardware , 2007, 2007 IEEE International Test Conference.

[13]  Giovanni Squillero,et al.  Automatic test program generation: a case study , 2004, IEEE Design & Test of Computers.

[14]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.

[15]  Qiang Xu,et al.  On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Hon Wai Leong,et al.  On the reconfiguration of degradable VLSI/WSI arrays , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Masaru Fukushi,et al.  A genetic approach for the reconfiguration of degradable processor arrays , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[18]  Itsuo Takanami,et al.  Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions , 2000, IEEE Trans. Computers.

[19]  Itsuo Takanami,et al.  A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement , 2012, 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing.

[20]  Liu Zheng,et al.  Hybrid Communication Reconfigurable Network on Chip for MPSoC , 2010, 2010 24th IEEE International Conference on Advanced Information Networking and Applications.

[21]  Michail Maniatakos,et al.  Systematic Software-Based Self-Test for Pipelined Processors , 2008, IEEE Trans. Very Large Scale Integr. Syst..

[22]  Chor Ping Low,et al.  An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays , 2000, IEEE Trans. Computers.

[23]  Dimitris Gizopoulos,et al.  Effective software-based self-test strategies for on-line periodic testing of embedded processors , 2005 .

[24]  Masaru Fukushi,et al.  A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches , 2004, IEEE Transactions on Instrumentation and Measurement.

[25]  Wu Jigang,et al.  Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  E. Schenfeld,et al.  A reconfigurable interconnect fabric with optical circuit switch and software optimizer for stream computing systems , 2009, 2009 Conference on Optical Fiber Communication - incudes post deadline papers.

[27]  William Lindsay,et al.  FRITS - a microprocessor functional BIST method , 2002, Proceedings. International Test Conference.

[28]  Jacques Henri Collet,et al.  Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays , 2011, IEEE Transactions on Dependable and Secure Computing.

[29]  Wu Jigang,et al.  Reconfiguration algorithms for power efficient VLSI subarrays with four-port switches , 2006, IEEE Transactions on Computers.

[30]  Jens Sparsø,et al.  ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology , 2008 .

[31]  Sy-Yen Kuo,et al.  Efficient reconfiguration algorithms for degradable VLSI/WSI arrays , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[32]  Jizhou Sun,et al.  Non-Backtracking Reconfiguration Algorithm for Three-dimensional VLSI Arrays , 2012, 2012 IEEE 18th International Conference on Parallel and Distributed Systems.

[33]  Li Zhang,et al.  Fault-Tolerant Meshes with Small Degree , 2002, IEEE Trans. Computers.

[34]  John P. Morrison,et al.  Graph Partitioning for Reconfigurable Topology , 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium.

[35]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[36]  Sujit Dey,et al.  A scalable software-based self-test methodology for programmable processors , 2003, DAC '03.