Implementations of the Parallel-Sampling ADC Architecture
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[1] Chun-Ying Chen,et al. A 12b 3GS/s pipeline ADC with 500mW and 0.4 mm2 in 40nm digital CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.
[2] Boris Murmann. Low-Power Pipelined A/D Conversion , 2012 .
[3] Pascal Urard,et al. 22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[4] Pasquale Daponte,et al. IEEE Std.1658 - IEEE Standard for Terminology and Test Methods of Digital-to-Analog Converter Devices , 2012 .
[5] Ho-Young Lee,et al. 29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[6] Boris Murmann,et al. Background Calibration of Time-Interleaved Data Converters , 2011 .
[7] Stephen H. Lewis,et al. Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[8] Lin He,et al. A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.
[9] P. R. Gray,et al. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.
[10] T. Yamaji,et al. 55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
[11] Yu Lin,et al. An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[12] Dong-Young Chang. Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..
[13] Arthur van Roermund,et al. Design Criteria for Cyclic and Pipelined ADCs , 2007 .
[14] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..
[15] Claudio Nani,et al. A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.
[16] Jingbo Wang,et al. A 1GS/s 11b Time-Interleaved ADC in 0.13/spl mu/m CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[17] Andrew Morgan,et al. A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration , 2010, IEEE Journal of Solid-State Circuits.
[18] Behzad Razavi,et al. A 12-Bit 200-MHz CMOS ADC , 2009, IEEE Journal of Solid-State Circuits.
[19] Matthew Martin,et al. A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[20] Walt Kester,et al. The data conversion handbook , 2005 .
[21] M. Waltari,et al. A 10-bit 200 MS/s CMOS parallel pipeline A/D converter , 2001, Proceedings of the 26th European Solid-State Circuits Conference.
[22] Behzad Razavi,et al. A 10-bit 1-GHz 33-mW CMOS ADC , 2012, 2012 Symposium on VLSI Circuits (VLSIC).
[23] Hans Hegt,et al. An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals , 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).
[24] R. Engelbrecht,et al. DIGEST of TECHNICAL PAPERS , 1959 .
[25] Robert W. Brodersen,et al. A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing , 2010, IEEE Journal of Solid-State Circuits.
[26] L. R. Carley,et al. Analysis of switched-capacitor common-mode feedback circuit , 2003, IEEE Trans. Circuits Syst. II Express Briefs.
[27] Haruo Kobayashi,et al. Explicit analysis of channel mismatch effects in time-interleaved ADC systems , 2001 .
[28] Arthur H. M. van Roermund,et al. Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[29] Charles K. Sestok,et al. A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC , 2011, 2011 IEEE International Solid-State Circuits Conference.
[30] I. Mehr,et al. A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 2000 .
[31] Hae-Seung Lee,et al. A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration , 2014, IEEE Journal of Solid-State Circuits.
[32] Borivoje Nikolic,et al. A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS , 2012, 2012 Symposium on VLSI Circuits (VLSIC).
[33] J. Jacob Wikner,et al. CMOS Data Converters for Communications , 2000 .
[34] Behzad Razavi,et al. Design Considerations for Interleaved ADCs , 2013, IEEE Journal of Solid-State Circuits.