Application-Dependent Delay Testing of FPGAs

Testing of field-programmable gate array (FPGA) resources used for mapping a particular design (application-dependent testing) is a key factor in FPGA defect tolerance for yield enhancement and cost reduction as well as online testing in adaptive reliable computing. The majority of the FPGA real estate is dedicated to the interconnect network, and defects in the interconnects manifest themselves as delay faults. In this paper, a very thorough application-dependent interconnect delay testing technique is presented. Achieving a high coverage on path delay fault has been traditionally intractable for application-specific integrated circuits. However, by leveraging the reconfigurability of FPGAs, the presented technique is able to achieve 100% robust path delay coverage on all the paths in the design. This automatically results in 100% transition fault coverage. The required number of test configurations is two or four, depending on the structure of the design. Algorithms with linear time complexity are presented for automatic test configuration and test vector generation

[1]  Yervant Zorian,et al.  Testing the Interconnect of RAM-Based FPGAs , 1998, IEEE Des. Test Comput..

[2]  Andrzej Krasniewski.  Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices , 2003, FPL.

[3]  Charles E. Stroud,et al.  Built-in self-test of FPGA interconnect , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[4]  Russell Tessier,et al.  Diagnosis of interconnect faults in cluster-based FPGA architectures , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[5]  Gabriel Robins,et al.  New Performance-Driven FPGA Routing Algorithms , 1996, 32nd Design Automation Conference.

[6]  Andrzej Krasniewski.  Application-dependent testing of FPGA delay faults , 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

[7]  Charles E. Stroud,et al.  BIST-Based Delay-Fault Testing in FPGAs , 2003, J. Electron. Test..

[8]  Andrzej Krasniewski.  Testing FPGA delay faults in the system environment is very different from "ordinary" delay fault testing , 2001, Proceedings Seventh International On-Line Testing Workshop.

[9]  Yervant Zorian,et al.  IS-FPGA : a new symmetric FPGA architecture with implicit scan , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[10]  Carlos R. P. Hartmann,et al.  Dual-Mode Logic for Function-Independent Fault Testing , 1980, IEEE Transactions on Computers.

[11]  Fabrizio Lombardi,et al.  On the diagnosis of programmable interconnect systems: Theory and application , 1996, Proceedings of 14th VLSI Test Symposium.

[12]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[13]  Patrick Girard,et al.  Defect analysis for delay-fault BIST in FPGAs , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[14]  Nur A. Touba,et al.  Configuration self-test in FPGA-based reconfigurable systems , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[15]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[16]  Erik Chmelar,et al.  FPGA Interconnect Delay Fault Testing , 2003, ITC.

[17]  Melvin A. Breuer,et al.  High quality robust tests for path delay faults , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[18]  Hideo Fujiwara,et al.  A test methodology for interconnect structures of LUT-based FPGAs , 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

[19]  Mehdi Baradaran Tahoori,et al.  Techniques and algorithms for fault grading of FPGA interconnect test configurations , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  E. Chmelaf.  Fpga interconnect delay fault testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[21]  Jian Xu,et al.  Novel technique for built-in self-test of FPGA interconnects , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[22]  Weiping Shi,et al.  K longest paths per gate (KLPG) test generation for scan-based sequential circuits , 2004, 2004 International Conferce on Test.

[23]  Melvin A. Breuer,et al.  The BALLAST Methodology for Structured Partial Scan Design , 1990, IEEE Trans. Computers.

[24]  Premachandran R. Menon,et al.  BIST-based delay path testing in FPGA architectures , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[25]  Mehdi B. Tahoori,et al.  Interconnect delay testings of designs on programmable logic devices , 2004 .

[26]  Edward J. McCluskey,et al.  Multiple-output propagation transition fault test , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[27]  Mehdi Baradaran Tahoori,et al.  Diagnosis of open defects in FPGA interconnect , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[28]  Mehdi Baradaran Tahoori,et al.  Automatic configuration generation for FPGA interconnect testing , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[29]  Michel Renovell.  Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs , 2003, J. Circuits Syst. Comput..

[30]  Shahin Toutounchi,et al.  FPGA test and coverage , 2002, Proceedings. International Test Conference.

[31]  Fabrizio Lombardi,et al.  A diagnosis method for interconnects in SRAM based FPGAs , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[32]  Nur A. Touba,et al.  A low cost approach for detecting, locating, and avoiding interconnect faults in FPGA-based reconfigurable systems , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).