A built-in timing parametric measurement unit

A built-in parametric measurement circuit is proposed for time-interval measurement and set-up/hold time measurement. The main idea is based on the dual-slope technique. The minimum resolution is set by resistor array configuration, which is 1/16 clock period in this paper, and easily extendable to desired precision. The imperfection, including the offset voltage and the settling time, is considered to improve the accuracy. Moreover, a simple calibration method is proposed to reduce the measuring error. Experiments on the SRAM access time measurement and the register set-up/hold time measurement show the practicality of the proposed unit.

[1]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[2]  Shen-Iuan Liu,et al.  A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[3]  Aubin Roy,et al.  BIST for phase-locked loops in digital applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[4]  Jing-Reng Huang,et al.  A low-cost CMOS time interval measurement core , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[5]  Ananta K. Majhi,et al.  Automated AC (timing) characterization for digital circuit testing , 1998, Proceedings Eleventh International Conference on VLSI Design.

[6]  R. Chandramouli,et al.  Testing systems on a chip , 1996 .

[7]  J. Kostamovaara,et al.  A low-power CMOS time-to-digital converter , 1995 .

[8]  T. Rahkonen,et al.  Time interval measurements using time-to-voltage conversion with built-in dual-slope A/D conversion , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[9]  Yervant Zorian,et al.  On using IEEE P1500 SECT for test plug-n-play , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[10]  Kwang-Ting Cheng,et al.  An on-chip short-time interval measurement technique for testing high-speed communication links , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[11]  Yervant Zorian,et al.  Towards a standard for embedded core test: an example , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).