Real-Time Communication over Wormhole-Switched On-Chip Networks
暂无分享,去创建一个
[1] Henry Hoffmann,et al. On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.
[2] Stefan M. Petters,et al. NoC contention analysis using a branch-and-prune algorithm , 2014, ACM Trans. Embed. Comput. Syst..
[3] Stefan M. Petters,et al. EDF as an arbitration policy for wormhole-switched priority-preemptive NoCs — Myth or fact? , 2014, 2014 International Conference on Embedded Software (EMSOFT).
[4] A. Burns,et al. Improvement of Schedulability Analysis with a Priority Share Policy in On-Chip Networks , 2009 .
[5] Laure Abdallah,et al. Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores , 2015, 10th IEEE International Symposium on Industrial Embedded Systems (SIES).
[6] Lei Gao,et al. An accurate and efficient performance analysis approach based on queuing model for network on chip , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[7] Stefan M. Petters,et al. Are virtual channels the bottleneck of priority-aware wormhole-switched NoC-based many-cores? , 2013, RTNS '13.
[8] Jean-Yves Le Boudec,et al. Network Calculus: A Theory of Deterministic Queuing Systems for the Internet , 2001 .
[9] Alan Burns,et al. Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).
[10] Meng Liu,et al. Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs , 2017, 2017 25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).
[11] Marcelo Lubaszewski,et al. Reliability, Availability and Serviceability of Networks-on-Chip , 2011 .
[12] Alan Burns,et al. Schedulability analysis and task mapping for real-time on-chip communication , 2010, Real-Time Systems.
[13] Jérôme Ermont,et al. Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures , 2016, 2016 IEEE World Conference on Factory Communication Systems (WFCS).
[14] Mathai Joseph,et al. Finding Response Times in a Real-Time System , 1986, Comput. J..
[15] Radu Marculescu,et al. SVR-NoC: A performance analysis tool for Network-on-Chips using learning-based support vector regression model , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[16] Kees Goossens,et al. AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.
[17] William J. Dally. Virtual-channel flow control , 1990, ISCA '90.
[18] Christian Fraboul,et al. A method of computation for worst-case delay analysis on SpaceWire networks , 2009, 2009 IEEE International Symposium on Industrial Embedded Systems.
[19] Benoît Dupont de Dinechin,et al. Time-critical computing on a single-chip massively parallel processor , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[20] Martin Schoeberl,et al. Time-division multiplexing vs network calculus: a comparison , 2015, RTNS.
[21] Chang-Gun Lee,et al. Stochastic analysis of periodic real-time systems , 2002, 23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002..
[22] Laure Abdallah,et al. Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip , 2016, 2016 28th Euromicro Conference on Real-Time Systems (ECRTS).
[23] Mary Shaw,et al. The coming-of-age of software architecture research , 2001, Proceedings of the 23rd International Conference on Software Engineering. ICSE 2001.
[24] Rolf Ernst,et al. Worst-case communication time analysis of networks-on-chip with shared virtual channels , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[25] Lionel M. Ni,et al. A survey of wormhole routing techniques in direct networks , 1993, Computer.
[26] Alan Burns,et al. Real-Time Communication Analysis with a Priority Share Policy in On-Chip Networks , 2009, 2009 21st Euromicro Conference on Real-Time Systems.
[27] Axel Jantsch,et al. An Analytical Latency Model for Networks-on-Chip , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[28] Christian Fraboul,et al. A Network Calculus Model for SpaceWire Networks , 2011, 2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications.
[29] Meng Liu,et al. A Stochastic Response Time Analysis for Communications in On-chip Networks , 2015, 2015 IEEE 21st International Conference on Embedded and Real-Time Computing Systems and Applications.
[30] William J. Dally,et al. Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.
[31] Martin Schoeberl,et al. A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.
[32] Leandro Soares Indrusiak,et al. End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration , 2014, J. Syst. Archit..
[33] Wenhua Dou,et al. Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[34] Rolf Ernst,et al. System level performance analysis - the SymTA/S approach , 2005 .
[35] Hiren D. Patel,et al. SLA: A Stage-Level Latency Analysisfor Real-Time Communicationin a Pipelined Resource Model , 2015, IEEE Transactions on Computers.
[36] F. P. Brooks,et al. Grasping reality through illusion—interactive graphics serving science , 1988, CHI '88.
[37] Fei Wu,et al. Real-time analysis for wormhole NoC: Revisited and revised , 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).
[38] Hermann Kopetz,et al. Concepts of Switching in the Time-Triggered Network-on-Chip , 2008, 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.