A room temperature 0.1 /spl mu/m CMOS on SOI

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >

[1]  E. Dubois,et al.  Anomalous voltage overshoot during turn-off of thin-film n-channel SOI MOSFETs , 1993, IEEE Electron Device Letters.

[2]  J. Colinge.  Reduction of kink effect in thin-film SOI MOSFETs , 1988, IEEE Electron Device Letters.

[3]  K. A. Jenkins,et al.  Measurement of SOI MOSFET I-V characteristics without self-heating , 1994, Proceedings. IEEE International SOI Conference.

[4]  M. Matloubian.  Smart body contact for SOI MOSFETs , 1989, IEEE SOS/SOI Technology Conference.

[5]  A. Gnudi,et al.  Investigation of the impact ionization in the hydrodynamic model , 1993 .

[6]  B. Davari,et al.  High-performance devices for a 0.15- mu m CMOS technology , 1993, IEEE Electron Device Letters.

[7]  Rajiv V. Joshi,et al.  A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture , 1991 .

[8]  Y. Taur,et al.  Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing , 1990, International Technical Digest on Electron Devices.

[9]  M. Matloubian,et al.  Single-transistor latch in SOI MOSFETs , 1988, IEEE Electron Device Letters.

[10]  E. M. Buturla,et al.  Finite-element analysis of semiconductor devices: the FIELDAY program , 1981 .

[11]  James D. Hayden,et al.  Optimization of two-dimensional collector doping profiles for submicron BiCMOS technologies , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[12]  J.-P. Colinge,et al.  Thin-film SOI technology: the solution to many submicron CMOS problems , 1989, International Technical Digest on Electron Devices Meeting.

[13]  B. Davari,et al.  Indium channel implant for improved short-channel behavior of submicrometer NMOSFETs , 1993, IEEE Electron Device Letters.

[14]  G. G. Shahidi,et al.  High-performance CMOS fabricated on ultrathin BESOI with sub-10 nm ttv , 1993, Proceedings of 1993 IEEE International SOI Conference.