A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems

This paper presents a space reuse strategy for flash translation layers in SLC nand flash storage systems. The basic idea is to prevent a block with many free pages from being erased in a merge operation. The preserved blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts of each block in a nand flash are enhanced. By employing the reuse strategy, we propose a reuse-aware flash translation layer (FTL) called reuse-aware NFTL (RNFTL) to improve the endurance and space utilization of single level cell (SLC) nand flash. We provide the performance analysis of RNFTL for frequent update operations and sequential write operations, and theoretically compare RNFTL with representative FTL schemes. We also discuss the opportunity to apply the reuse strategy in log-block-based FTL schemes. To the best of our knowledge, this is the first work to employ a space reuse strategy in FTLs to improve the space utilization and endurance of nand flash. The experiments have been conducted on a set of traces collected from real workload in daily life. The results show that the space reuse strategy can effectively improve space utilization, block lifetime and wear-leveling compared with the previous work.

[1]  Meng Wang,et al.  RNFTL: a reuse-aware NAND flash translation layer for flash memory , 2010, LCTES '10.

[2]  Zili Shao,et al.  An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems , 2011, 2011 Design, Automation & Test in Europe.

[3]  Tei-Wei Kuo,et al.  A space-efficient caching mechanism for flash-memory address translation , 2006, Ninth IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'06).

[4]  Youngjae Kim,et al.  DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.

[5]  Tei-Wei Kuo,et al.  An Efficient B-Tree Layer for Flash-Memory Storage Systems , 2003, RTCSA.

[6]  Sang-Won Lee,et al.  A log buffer-based flash translation layer using fully-associative sector translation , 2007, TECS.

[7]  Tei-Wei Kuo,et al.  Configurable NAND flash translation layer , 2006, IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC'06).

[8]  Tei-Wei Kuo,et al.  Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[9]  Jongmoo Choi,et al.  Block recycling schemes and their cost-based optimization in nand flash memory based storage system , 2007, EMSOFT '07.

[10]  Dongkun Shin,et al.  KAST: K-associative sector translation for NAND flash memory in real-time systems , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[11]  阿米尔·班 Flash File System , 1994 .

[12]  Sang-Won Lee,et al.  A survey of Flash Translation Layer , 2009, J. Syst. Archit..

[13]  Tei-Wei Kuo,et al.  An efficient management scheme for large-scale flash-memory storage systems , 2004, SAC '04.

[14]  Heeseung Jo,et al.  A group-based wear-leveling algorithm for large-capacity flash memory storage systems , 2007, CASES '07.

[15]  Heeseung Jo,et al.  A superblock-based flash translation layer for NAND flash memory , 2006, EMSOFT '06.

[16]  Tei-Wei Kuo,et al.  A Real-Time Garbage Collection Mechanism for Flash-Memory Stroage Systems in Embedded Systems , 2002 .

[17]  Tei-Wei Kuo,et al.  Special Issues in Flash , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[18]  Tei-Wei Kuo,et al.  The Behavior Analysis of Flash-Memory Storage Systems , 2008, 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC).

[19]  Tony Givargis,et al.  Performance improvement of block based NAND flash translation layer , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[20]  Li-Pin Chang,et al.  On efficient wear leveling for large-scale flash-memory storage systems , 2007, SAC '07.

[21]  Chanik Park,et al.  A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

[22]  Tei-Wei Kuo,et al.  An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[23]  Sang Lyul Min,et al.  A space-efficient flash translation layer for CompactFlash systems , 2002, IEEE Trans. Consumer Electron..