A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.

[1]  F. Kuttner,et al.  A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.

[2]  Michael P. Flynn,et al.  A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS , 2006, IEEE Custom Integrated Circuits Conference 2006.

[3]  M.-C.F. Chang,et al.  A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging , 2005, IEEE Journal of Solid-State Circuits.

[4]  O. Hidri,et al.  A 1.8V 1.6GS/s 8b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[5]  S. Pavan,et al.  A Distortion Compensating Flash Analog-to-Digital Conversion Technique , 2006, IEEE Journal of Solid-State Circuits.