Efficient Designs for Adder Comparator

When two fixed-point binary values are compared, in average, only two bit positions are dominant to decide its result. To exploit this property in efficient arithmetic operations two types of addition and comparison circuits are considered. A parallel input design that utilizes dynamic asynchronous mechanisms has been implemented by MOSIS AMI 1.5mum process. The other design assumes serial inputs and has internal clocking with asynchronous input/output interface.