An Adaptive Viterbi Decoder Architecture Using Reduced State Transition Paths

The development of a new hardware structure which can implement the viterbi algorithm efficiently is required for applications such as a software radio because the viterbi algorithm, which is an error correction code function for the second and the third generation of mobile communication, needs a lot of arithmetic operations. The length of K in the viterbi algorithm different from each standard, for examples, K=7 in case of IS-95 standard and GSM standard, and K=9 in case of WCDMA and CDMA2000. In this paper, we propose a new hardware structure of an adaptive viterbi decoder which can decode the constraint length in K=3~9 and the data rate in 1/2 ~ 1/3. Prototyping results targeted to Altera Cyclon EPIC20F400C8, shows that the proposed hardware structure needs maximum 19,276 logic elements and power dissipation of 222.6 mW.