Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults

The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, 6n, where n is the number of nets patterns are drastically reduced to a constant number 6D, where D indicates the effective distance among interconnect nets. The test quality for static and crosstalk faults are completely preserved with 6D patterns.

[1]  Sungho Kang,et al.  A new maximal diagnosis algorithm for interconnect test , 2004, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Rajesh Kumar,et al.  Interconnect and noise immunity design for the Pentium 4 processor , 2003, DAC.

[3]  Wu-Tung Cheng,et al.  Optimal diagnostic methods for wiring interconnects , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Jaehoon Song,et al.  Efficient Interconnect Test Patterns for Crosstalk and Static Faults , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Sandeep K. Gupta,et al.  Enhanced crosstalk fault model and methodology to generate tests for arbitrary inter-core interconnect topology , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[6]  Sujit Dey,et al.  LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects , 2003, J. Electron. Test..

[7]  Chandra Tirumurti,et al.  On modeling crosstalk faults , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Cecilia Metra,et al.  Exploiting ECC redundancy to minimize crosstalk impact , 2005, IEEE Design & Test of Computers.

[9]  Sujit Dey,et al.  Self-test methodology for at-speed test of crosstalk in chip interconnects , 2000, DAC.

[10]  Sujit Dey,et al.  Fault modeling and simulation for crosstalk in system-on-chip interconnects , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[11]  Vinod K. Agarwal,et al.  Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[12]  Sujit Dey,et al.  Fault-coverage analysis techniques of crosstalk in chip interconnects , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Najmi T. Jarwala,et al.  A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[14]  Melvin A. Breuer,et al.  Process aggravated noise (PAN): new validation and test problems , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[15]  Abhijit Chatterjee,et al.  Switching activity generation with automated BIST synthesis forperformance testing of interconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Cecilia Metra,et al.  Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects , 2006, Proceedings of the Design Automation & Test in Europe Conference.