Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparative study and experimental results

In this paper two lost-cost solutions for providing error detection capabilities to processor-based systems are compared. The effects of SEUs and SETs is studied through simulation-based fault injection which is used to compare the error detection capabilities of a hardware-implemented solution, based on parity code, with that of a software-implemented solution based on source-level code modification. Radiation testing experiments confirmed the obtained results.

[1]  Jiri Gaisler Evaluation of a 32-bit microprocessor with built-in concurrent error-detection , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[2]  Lorena Anghel,et al.  Cost reduction and evaluation of temporary faults detecting technique , 2000, DATE '00.

[3]  R. Velazco,et al.  Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors , 2000 .

[4]  Raoul Velazco,et al.  THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment , 1998 .

[5]  Elizabeth M. Rudnick,et al.  A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults , 1996, IEEE Trans. Computers.

[6]  Marco Torchiano,et al.  An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[7]  S. Rezgui,et al.  Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection , 2000 .

[8]  Michael Nicolaidis Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[9]  Lloyd W. Massengill,et al.  Cosmic and terrestrial single-event radiation effects in dynamic random access memories , 1996 .

[10]  Heinrich Theodor Vierhaus,et al.  Generating reliable embedded processors , 1998, IEEE Micro.

[11]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[12]  Suku Nair,et al.  Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection , 1999, IEEE Trans. Parallel Distributed Syst..

[13]  Alfredo Benso,et al.  A C/C++ source-to-source compiler for dependable applications , 2000, Proceeding International Conference on Dependable Systems and Networks. DSN 2000.

[14]  Edward J. McCluskey,et al.  Software-implemented EDAC protection against SEUs , 2000, IEEE Trans. Reliab..

[15]  Jacob A. Abraham,et al.  Algorithm-Based Fault Tolerance for Matrix Operations , 1984, IEEE Transactions on Computers.

[16]  Bharat L. Bhuva,et al.  Analysis of single-event effects in combinational logic-simulation of the AM2901 bitslice processor , 2000 .