A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance

Synchronizers play a key role in multiclock domains systems on chip and their performance is usually measured by the mean-time between failures (MTBF) of the system. Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling for library flip-flop circuits in 65 nm and below. This degradation of parameters becomes critical when the system is operated under extreme supply voltage and temperature conditions. In this paper, we study the behavior of synchronizers in a broad range of supply voltage and temperature conditions. A new model for the metastability time constant (τ), the metastability window (TW), and MTBF is presented. We show a detailed comparison of model, measurements, and simulations for different technology nodes and discuss implications for modern synchronization systems. We propose design guidelines that account for supply voltage and temperature variations and determine the correct number of synchronizer stages required for target MTBF.

[1]  Paul Ampadu,et al.  Managing Temperature Effects in Nanoscale Adaptive Systems , 2011 .

[2]  Suwen Yang,et al.  Computing Synchronizer Failure Probabilities , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[3]  C. L. Portmann,et al.  Metastability in CMOS library elements in reduced supply and technology scaled applications , 1995 .

[4]  J. Kalisz,et al.  Metastability tests of flip-flops in programmable digital circuits , 2006, Microelectron. J..

[5]  Salomon Beer,et al.  MTBF Bounds for Multistage Synchronizers , 2013, 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems.

[6]  Ran Ginosar,et al.  An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[7]  Suwen Yang,et al.  Synchronizer Performance in Deep Sub-Micron Technology , 2011, 2011 17th IEEE International Symposium on Asynchronous Circuits and Systems.

[8]  David Li,et al.  Comparative analysis and study of metastability on high-performance flip-flops , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[9]  Alexandre Yakovlev,et al.  Measuring Deep Metastability and Its Effect on Synchronizer Performance , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Thomas J. Chaney,et al.  Measured Flip-Flop Responses to Marginal Triggering , 1983, IEEE Transactions on Computers.

[11]  Z. Jachna,et al.  Dual-edge late-transition detector for testing the metastability effect in flip-flops , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

[12]  Antonio Cantoni,et al.  Metastable Behavior in Digital Systems , 1987, IEEE Design & Test of Computers.

[13]  Jun Zhou,et al.  Adapting Synchronizers to the Effects of on Chip Variability , 2008, 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems.

[14]  Kouichi Kanda,et al.  Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[15]  Jun Zhou,et al.  Extending Synchronization from Super-Threshold to Sub-threshold Region , 2010, 2010 IEEE Symposium on Asynchronous Circuits and Systems.

[16]  Avinoam Kolodny,et al.  The devolution of synchronizers , 2010 .

[17]  Ran Ginosar,et al.  Timing measurements of synchronization circuits , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[18]  David J. Kinniment,et al.  Synchronization circuit performance , 2002 .

[19]  Paul Ampadu,et al.  A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits , 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[20]  S. T. Flannagan,et al.  Synchronization reliability in CMOS technology , 1985 .

[21]  Ran Ginosar,et al.  Metastability challenges for 65nm and beyond; simulation and measurements , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[22]  Jun Zhou,et al.  A robust synchronizer , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[23]  J. E. DENNIS,et al.  A Trust-Region Approach to Nonlinear Systems of Equalities and Inequalities , 1999, SIAM J. Optim..

[24]  Madhav P. Desai,et al.  Impact of technology scaling on metastability performance of CMOS synchronizing latches , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[25]  F. J. Anscombe,et al.  Graphs in Statistical Analysis , 1973 .

[26]  E. Nowak,et al.  High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev , 2006 .

[27]  C. Dike,et al.  Miller and noise effects in a synchronizing flip-flop , 1999 .

[28]  Shi-Jie Wen,et al.  Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS , 2012, IEEE Trans. Circuits Syst. I Regul. Pap..

[29]  A. Albicki,et al.  Analysis of mesastable operation in RS CMOS flip-flops , 1987 .

[30]  Vaughn Betz,et al.  A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs , 2010, FPGA '10.

[31]  Karolj Skala,et al.  Metastability testing at FPGA circuit design using propagation time characterization , 2010, 2010 East-West Design & Test Symposium (EWDTS).

[32]  Charles E. Molnar,et al.  Anomalous Behavior of Synchronizer and Arbiter Circuits , 1973, IEEE Transactions on Computers.

[33]  Kiyoo Itoh,et al.  Supply voltage scaling for temperature insensitive CMOS circuit operation , 1998 .

[34]  Ran Ginosar,et al.  Metastability and Synchronizers: A Tutorial , 2011, IEEE Design & Test of Computers.

[35]  T. C. Tang.  Experimental studies of metastability behaviors of sub-micron CMOS ASIC flip flops , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[36]  P. R. Bevington,et al.  Data Reduction and Error Analysis for the Physical Sciences , 1969 .

[37]  I. Filanovsky,et al.  Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits , 2001 .

[38]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2007 .

[39]  Jun Zhou,et al.  On-Chip Measurement of Deep Metastability in Synchronizers , 2008, IEEE Journal of Solid-State Circuits.

[40]  Antonio Cantoni,et al.  Characterization of a Flip-Flop Metastability Measurement Method , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[41]  D. J. Kinniment.  Synchronization and Arbitration in Digital Systems , 2008 .

[42]  Kouichi Kanda,et al.  Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs , 1999 .