Interconnect layout optimization under higher order RLC model forMCM designs

In this paper, we study the interconnect layout optimization problem under a higher order resistance-inductance-capacitance model to optimize not only delay, but also waveform for interconnects with nonmonotone signal response in the context of multichip-module global routing. We propose a unified approach that considers topology optimization and waveform optimization simultaneously. Using a new incremental moment-computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Our algorithm considers a large class of routing topologies, ranging from shortest path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required arrival-time Steiner (RATS) trees, providing smooth tradeoffs among signal delay, waveform, and routing area. When combined with the MINOTAUR MCM global router (Cong and Madden, 1998), (Madden, 1998) that we have developed, the RATS-tree solutions prove to be effective in reducing overall routing congestion.

[1]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[2]  Mary Jane Irwin,et al.  An edge-based heuristic for Steiner routing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  D. F. Wong,et al.  Shaping a VLSI wire to minimize delay using transmission line model , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[4]  D. F. Wong,et al.  Optimal wire-sizing formula under the Elmore delay model , 1996, 33rd Design Automation Conference Proceedings, 1996.

[5]  Jason Cong,et al.  An Efficient Multilayer MCM Router Based on Four-Via Routing , 1993, 30th ACM/IEEE Design Automation Conference.

[6]  Andrew B. Kahng,et al.  Near-optimal critical sink routing tree constructions , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Jason Cong,et al.  Performance driven multi-layer general area routing for PCB/MCM designs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[8]  John P. Fishburn,et al.  Shaping a VLSI wire to minimize Elmore delay , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[9]  Jason Cong,et al.  Optimal wiresizing under Elmore delay model , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Jason Cong,et al.  An efficient multilayer MCM router based on four-via routing , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Hai Zhou,et al.  Simultaneous routing and buffer insertion with restrictions on buffer locations , 1999, DAC '99.

[12]  Xianlong Hong,et al.  Performance-Driven Steiner Tree Algorithms for Global Routing , 1993, 30th ACM/IEEE Design Automation Conference.

[13]  M. Hanan,et al.  On Steiner’s Problem with Rectilinear Distance , 1966 .

[14]  Sachin S. Sapatnekar,et al.  Non-Hanan routing , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Lawrence T. Pileggi,et al.  Transmission Line Synthesis , 1995, 32nd Design Automation Conference.

[16]  Ernest S. Kuh,et al.  Exact moment matching model of transmission lines and application to interconnect delay estimation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Chung-Kuan Cheng,et al.  New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing , 1996, DAC '96.

[18]  Andrew B. Kahng,et al.  A new class of iterative Steiner tree heuristics with good performance , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  J. Cong,et al.  Optimal wiresizing under the distributed Elmore delay model , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[20]  Lawrence T. Pileggi,et al.  OTTER: Optimal Termination of Transmission lines Excluding Radiation , 1994, 31st Design Automation Conference.

[21]  D. Huang.  On the bounded-skew routing tree problem , 1995, DAC 1995.

[22]  Sachin S. Sapatnekar,et al.  Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model , 1999, ISPD '99.

[23]  Chung-Kuan Cheng,et al.  A new layout-driven timing model for incremental layout optimization , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[24]  Jason Cong,et al.  High-performance vlsi global routing , 1998 .

[25]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Lawrence T. Pillage,et al.  Rc Interconnect Synthesis-a Moment Fitting Approach , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[27]  Jason Cong,et al.  Fast optimal algorithms for the minimum rectilinear Steiner arborescence problem , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[28]  Jason Cong,et al.  Optimal wiresizing under the distributed Elmore delay model , 1993, ICCAD '93.

[29]  Ernest S. Kuh,et al.  A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies , 1996, Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893).

[30]  Chung-Kuan Cheng,et al.  Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .

[31]  Jason Cong,et al.  Provably good performance-driven global routing , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[32]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[33]  J. Cong,et al.  Interconnect layout optimization under higher-order RLC model , 1997, ICCAD 1997.

[34]  Lawrence T. Pileggi,et al.  Constrained multivariable optimization of transmission lines with general topologies , 1995, ICCAD.

[35]  Cheng-Kok Koh,et al.  Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures , 2000, ACM Great Lakes Symposium on VLSI.

[36]  Jason Cong,et al.  Performance-Driven Interconnect Design Based on Distributed RC Delay Model , 1993, 30th ACM/IEEE Design Automation Conference.

[37]  Jason Cong,et al.  Interconnect layout optimization under higher-order RLC model , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[38]  Andrew B. Kahng,et al.  Two-pole analysis of interconnection trees , 1995, Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95).