Test Time Minimization for Hybrid BIST of Core-Based Systems

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper, we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.

[1]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[2]  Raimund Ubar,et al.  A hybrid BIST architecture and its optimization for SoC testing , 2002, Proceedings International Symposium on Quality Electronic Design.

[3]  Raimund Ubar,et al.  Test cost minimization for hybrid BIST , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[4]  H. Yasuura,et al.  Analysis and minimization of test time in a combined BIST and external test approach , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[5]  John P. Hayes,et al.  Testing ICs: Getting to the Core of the Problem , 1996, Computer.

[6]  David Flynn,et al.  AMBA: enabling reusable on-chip designs , 1997, IEEE Micro.

[7]  Anupam Basu,et al.  A new test scheduling algorithm for VLSI systems , 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

[8]  Erik G. Larsson,et al.  An Integrated Framework for the Design and Optimization of SOC Test Solutions , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[9]  Krishnendu Chakrabarty,et al.  Accepted for Publication in Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems Test Scheduling for Core-based Systems Using Mixed-integer Linear Programming , 2000 .

[10]  Mircea Vladutiu,et al.  A comparison of classical scheduling approaches in power-constrained block-test scheduling , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[11]  Yervant Zorian,et al.  Testing Embedded-Core-Based System Chips , 1999, Computer.

[12]  Raimund Ubar,et al.  Fast test cost calculation for hybrid BIST in digital systems , 2001, Proceedings Euromicro Symposium on Digital Systems Design.

[13]  Krishnendu Chakrabarty.  Test scheduling for core-based systems , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[14]  Vishwani D. Agrawal,et al.  Scheduling tests for VLSI systems under power constraints , 1997, IEEE Trans. Very Large Scale Integr. Syst..