Full-chip lithography simulation and design analysis: how OPC is changing IC design

Ten years ago Model-Based OPC (MB-OPC) was a research project of questionable usefulness, seen possibly as a fix until the next generation stepper was available. Today MB-OPC is one of the key technologies enabling 90nm production. In that brief span many technological challenges were resolved to allow MB-OPC to be performed on full chip layout with manageable computer resources and turnaround times. As MB-OPC has transitioned from a research to a production activity, several organizational challenges have arisen. Defining the steps and procedures involved in creating OPC techfiles has been necessary to allow the increased workload to be shared. Testing and documenting the OPC recipes has become a necessary discipline to ensure quality and repeatability in manufacturing. In addition to the engineers who create the OPC recipes, we now also have Fab OPC Engineers to support OPC verification and continuous improvement activities. Furthermore, the OPC process, i.e. the modification of the layout to account for the manufacturing process, has provided a tantalizing link between the design, process development and yield engineering communities. The EDA framework appears to provide a common language, however we are just beginning to ask the right questions to allow us to unlock the potential that appears so close. The paper will begin with a historical overview of the development of MB-OPC and describe the seemingly overwhelming obstacles, both computational and in mask fabrication that had to be overcome. The second part of the paper will deal with some of the problems that have arisen as MB-OPC has become a critical technology for high volume production. The final part of the paper will discuss how MB-OPC has changed the way that Lithography, Integration and Design engineers interact. Some examples of design/process interaction will be given as well as a discussion of future developments.